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[/] [phr/] [branches/] [placas_1.0/] [placas/] [FPGA/] [fpga.cmp] - Diff between revs 11 and 17

Rev 11	Rev 17
Line 1...	Line 1...
`Cmp-Mod V01 Created by CvPCB (2010-03-14)-final date = jue 26 abr 2012 22:31:26 ART`	`Cmp-Mod V01 Genere par PcbNew le dom 17 jun 2012 13:25:19 ART`

`BeginCmp`	`BeginCmp`
`TimeStamp = /4F4D3964;`	`TimeStamp = /4F4D3964;`
`Reference = C1;`	`Reference = C1;`
`ValeurCmp = C_clk;`	`ValeurCmp = C_clk;`
Line 212...	Line 212...

`BeginCmp`	`BeginCmp`
`TimeStamp = /4F4807B3;`	`TimeStamp = /4F4807B3;`
`Reference = P1;`	`Reference = P1;`
`ValeurCmp = A;`	`ValeurCmp = A;`
`IdModule = 1X20;`	`IdModule = 1X20_MOD;`
`EndCmp`	`EndCmp`

`BeginCmp`	`BeginCmp`
`TimeStamp = /4F480E3E;`	`TimeStamp = /4F480E3E;`
`Reference = P2;`	`Reference = P2;`
`ValeurCmp = B;`	`ValeurCmp = B;`
`IdModule = 1X20;`	`IdModule = 1X20_MOD;`
`EndCmp`	`EndCmp`

`BeginCmp`	`BeginCmp`
`TimeStamp = /4F4D2C3A;`	`TimeStamp = /4F4D2C3A;`
`Reference = P3;`	`Reference = P3;`
`ValeurCmp = JTAG;`	`ValeurCmp = JTAG;`
`IdModule = 1X06;`	`IdModule = PIN_ARRAY-6X1;`
`EndCmp`	`EndCmp`

`BeginCmp`	`BeginCmp`
`TimeStamp = /4F47FC62;`	`TimeStamp = /4F47FC62;`
`Reference = P4;`	`Reference = P4;`
Line 303...	Line 303...

`BeginCmp`	`BeginCmp`
`TimeStamp = /4F4801A4;`	`TimeStamp = /4F4801A4;`
`Reference = SW1;`	`Reference = SW1;`
`ValeurCmp = RESET_PROG;`	`ValeurCmp = RESET_PROG;`
`IdModule = SW_PUSH-12mm;`	`IdModule = SW_PUSH_SMALL;`
`EndCmp`	`EndCmp`

`BeginCmp`	`BeginCmp`
`TimeStamp = /4F4675A1;`	`TimeStamp = /4F4675A1;`
`Reference = U1;`	`Reference = U1;`