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Subversion Repositories phr

[/] [phr/] [branches/] [placas_1.0/] [placas/] [FPGA/] [fpga.sch] - Diff between revs 5 and 10

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Rev 5	Rev 10
Line 1...	Line 1...
`EESchema Schematic File Version 2 date mar 20 mar 2012 21:35:54 ART`	`EESchema Schematic File Version 2 date mar 24 abr 2012 21:18:48 ART`
`LIBS:power`	`LIBS:power`
`LIBS:device`	`LIBS:device`
`LIBS:transistors`	`LIBS:transistors`
`LIBS:conn`	`LIBS:conn`
`LIBS:linear`	`LIBS:linear`
Line 31...	Line 31...
`LIBS:xilinx_virtexii-xc2v80&flashprom`	`LIBS:xilinx_virtexii-xc2v80&flashprom`
`LIBS:tps75003_pm`	`LIBS:tps75003_pm`
`LIBS:pcb_hole`	`LIBS:pcb_hole`
`LIBS:osc`	`LIBS:osc`
`LIBS:fpga-cache`	`LIBS:fpga-cache`
`EELAYER 25 0`	`EELAYER 24 0`
`EELAYER END`	`EELAYER END`
`$Descr A4 11700 8267`	`$Descr A4 11700 8267`
`encoding utf-8`
`Sheet 1 1`	`Sheet 1 1`
`Title "Adaptador FPGA"`	`Title "Adaptador FPGA"`
`Date "20 mar 2012"`	`Date "25 apr 2012"`
`Rev "0.1"`	`Rev "0.1"`
`Comp "Proyecto: Plataforma de Hardware Reconfigurable"`	`Comp "Proyecto: Plataforma de Hardware Reconfigurable"`
`Comment1 "Autor: Luis Alberto Guanuco"`	`Comment1 "Autor: Luis Alberto Guanuco"`
`Comment2 ""`	`Comment2 ""`
`Comment3 ""`	`Comment3 ""`
`Comment4 ""`	`Comment4 ""`
`$EndDescr`	`$EndDescr`
	`Text Label 2450 950 0 60 ~ 0`
	`VCCAUX`
`$Comp`	`$Comp`
`L CAPAPOL Ca6`	`L CAPAPOL Ca6`
`U 1 1 4F69144A`	`U 1 1 4F69144A`
`P 6150 7300`	`P 6150 7300`
`F 0 "Ca6" H 6150 7400 50 0000 L CNN`	`F 0 "Ca6" H 6150 7400 50 0000 L CNN`
Line 1310...	Line 1311...
`1 8850 2750`	`1 8850 2750`
`-1 0 0 -1`	`-1 0 0 -1`
`$EndComp`	`$EndComp`
`Text Label 3900 950 0 60 ~ 0`	`Text Label 3900 950 0 60 ~ 0`
`VCCINT_1V2`	`VCCINT_1V2`
`Text Label 2400 950 0 60 ~ 0`
`VCCAUX`
`$EndSCHEMATC`	`$EndSCHEMATC`

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[/] [phr/] [branches/] [placas_1.0/] [placas/] [FPGA/] [fpga.sch] - Diff between revs 5 and 10