| Line 463... |
Line 463... |
\label{phr:gpio}
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\label{phr:gpio}
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\end{figure}
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\end{figure}
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|
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\begin{table}[h!]
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\begin{table}[h!]
|
\begin{center}
|
\begin{center}
|
\begin{tabular}{|r|c|c|l|}
|
\begin{tabular}{|c|c|c|c|c|c|}
|
\hline
|
\hline
|
\multicolumn{4}{ |c| }{\emph{Conector macho}} \\
|
\multicolumn{6}{ |c| }{\emph{Conector macho}} \\
|
\hline
|
\hline
|
\hline
|
\hline
|
\textbf{Conectado a} & \textbf{Pin} & \textbf{Pin} & \textbf{Conectado a} \\ \hline\hline
|
\textbf{Dir} & \textbf{Conectado a} & \textbf{Pin} & \textbf{Pin} & \textbf{Conectado a} & \textbf{Dir} \\ \hline\hline
|
FPGA Pin 39 & 1 & 2 & FPGA Pin 50 \\ \hline
|
E & FPGA Pin 39 & 1 & 2 & FPGA Pin 50 & E/S \\ \hline
|
FPGA Pin 37 & 3 & 4 & FPGA Pin 49 \\ \hline
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E/S & FPGA Pin 37 & 3 & 4 & FPGA Pin 49 & E/S \\ \hline
|
FPGA Pin 36 & 5 & 6 & FPGA Pin 46 \\ \hline
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E/S & FPGA Pin 36 & 5 & 6 & FPGA Pin 46 & E/S \\ \hline
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FPGA Pin 35 & 7 & 8 & FPGA Pin 34 \\ \hline
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E/S & FPGA Pin 35 & 7 & 8 & FPGA Pin 34 & E/S \\ \hline
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FPGA Pin 33 & 9 & 10 & FPGA Pin 32 \\ \hline
|
E/S & FPGA Pin 33 & 9 & 10 & FPGA Pin 32 & E/S \\ \hline
|
FPGA Pin 31 & 11 & 12 & FPGA Pin 30 \\ \hline
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E/S & FPGA Pin 31 & 11 & 12 & FPGA Pin 30 & E/S \\ \hline
|
FPGA Pin 29 & 13 & 14 & +3.3V \\ \hline
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E/S & FPGA Pin 29 & 13 & 14 & +3.3V & \\ \hline
|
FPGA Pin 28 & 15 & 16 & No conectado\\ \hline
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E/S & FPGA Pin 28 & 15 & 16 & No conectado & \\ \hline
|
FPGA Pin 27 & 17 & 18 & GND \\ \hline
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E/S & FPGA Pin 27 & 17 & 18 & GND & \\ \hline
|
\end{tabular}
|
\end{tabular}
|
\hspace{.1cm}
|
|
\begin{tabular}{|r|c|c|l|}
|
\vspace{0.5cm}
|
|
|
|
\begin{tabular}{|c|c|c|c|c|c|}
|
\hline
|
\hline
|
\multicolumn{4}{ |c| }{\emph{Conector hembra}} \\
|
\multicolumn{6}{ |c| }{\emph{Conector hembra}} \\
|
\hline
|
\hline
|
\hline
|
\hline
|
\textbf{Conectado a} & \textbf{Pin} & \textbf{Pin} & \textbf{Conectado a} \\ \hline\hline
|
\textbf{Dir} & \textbf{Conectado a} & \textbf{Pin} & \textbf{Pin} & \textbf{Conectado a} & \textbf{Dir} \\ \hline\hline
|
FPGA Pin 21 & 1 & 2 & FPGA Pin 20 \\ \hline
|
E & FPGA Pin 21 & 1 & 2 & FPGA Pin 20 & E/S \\ \hline
|
FPGA Pin 19 & 3 & 4 & FPGA Pin 16 \\ \hline
|
E/S & FPGA Pin 19 & 3 & 4 & FPGA Pin 16 & E/S \\ \hline
|
FPGA Pin 15 & 5 & 6 & FPGA Pin 13 \\ \hline
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E/S & FPGA Pin 15 & 5 & 6 & FPGA Pin 13 & E/S \\ \hline
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FPGA Pin 12 & 7 & 8 & +3.3V \\ \hline
|
E/S & FPGA Pin 12 & 7 & 8 & +3.3V & \\ \hline
|
FPGA Pin 10 & 9 & 10 & GND \\ \hline
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E/S & FPGA Pin 10 & 9 & 10 & GND & \\ \hline
|
\end{tabular}
|
\end{tabular}
|
\end{center}
|
\end{center}
|
\caption[Pines para las E/S de propósito general]{Conexión de los pines para las entradas/salidas de propósito general.}
|
\caption[Pines para las E/S de propósito general]{Conexión de los pines para las entradas/salidas de propósito general.}
|
\label{phr:GPIOpins}
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\label{phr:GPIOpins}
|
\end{table}
|
\end{table}
|
