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[/] [phr/] [trunk/] [doc/] [informe-tesis/] [reports/] [schedule_2013-03-20/] [schedule.aux] - Diff between revs 160 and 161

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Rev 160 Rev 161
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\newlabel{sec:xc3sprog-com-bas}{{3.2.3}{10}}
\newlabel{sec:xc3sprog-com-bas}{{3.2.3}{10}}
\bibcite{2012-SSE-FIUBA-NT01-00}{1}
\bibcite{2012-SSE-FIUBA-NT01-00}{1}
\bibcite{openocd-manual-autoprobing}{2}
\bibcite{openocd-manual-autoprobing}{2}
\acronymused{CPLD}
\acronymused{CPLD}
\acronymused{CPLD}
\acronymused{CPLD}
\@writefile{toc}{\contentsline {subsection}{\numberline {3.3}Programaci\IeC {\'o}n \ac {CPLD}}{12}}
\@writefile{toc}{\contentsline {subsection}{\numberline {3.3}Programaci\IeC {\'o}n \ac {CPLD}}{13}}
\@writefile{toc}{\contentsline {subsection}{\numberline {3.4}\textsl  {Debugging}}{12}}
\@writefile{toc}{\contentsline {subsection}{\numberline {3.4}\textsl  {Debugging}}{13}}
\@writefile{toc}{\contentsline {section}{\numberline {4}Documentaci\IeC {\'o}n}{12}}
\@writefile{toc}{\contentsline {section}{\numberline {4}Documentaci\IeC {\'o}n}{13}}
\acronymused{openocd}
\acronymused{openocd}
\acronymused{openocd}
\acronymused{openocd}
\@writefile{toc}{\contentsline {section}{\numberline {A}Acr\IeC {\'o}nimos}{13}}
\@writefile{toc}{\contentsline {section}{\numberline {A}Acr\IeC {\'o}nimos}{14}}
\newacro{PHR}[\AC@hyperlink{PHR}{PHR}]{Plataforma de Hardware Reconfigurable}
\newacro{PHR}[\AC@hyperlink{PHR}{PHR}]{Plataforma de Hardware Reconfigurable}
\newacro{openocd}[\AC@hyperlink{openocd}{OpenOCD}]{\textsl  {Open On-Chip Debugger}}
\newacro{openocd}[\AC@hyperlink{openocd}{OpenOCD}]{\textsl  {Open On-Chip Debugger}}
\newacro{jtag}[\AC@hyperlink{jtag}{JTAG}]{\textsl  {Joint Test Action Group}}
\newacro{jtag}[\AC@hyperlink{jtag}{JTAG}]{\textsl  {Joint Test Action Group}}
\newacro{TAP}[\AC@hyperlink{TAP}{TAP}]{\textsl  {Test Access Port}}
\newacro{TAP}[\AC@hyperlink{TAP}{TAP}]{\textsl  {Test Access Port}}
\newacro{SVF}[\AC@hyperlink{SVF}{SVF}]{\textsl  {Serial Vector Format}}
\newacro{SVF}[\AC@hyperlink{SVF}{SVF}]{\textsl  {Serial Vector Format}}
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\newacro{FPGA}[\AC@hyperlink{FPGA}{FPGA}]{\textsl  {Field Programmable Gate Array}}
\newacro{FPGA}[\AC@hyperlink{FPGA}{FPGA}]{\textsl  {Field Programmable Gate Array}}
\newacro{PROM}[\AC@hyperlink{PROM}{PROM}]{\textsl  {Programmable Read-Only Memory}}
\newacro{PROM}[\AC@hyperlink{PROM}{PROM}]{\textsl  {Programmable Read-Only Memory}}
\newacro{SO}[\AC@hyperlink{SO}{SO}]{sistema operativo}
\newacro{SO}[\AC@hyperlink{SO}{SO}]{sistema operativo}
\newacro{GPL}[\AC@hyperlink{GPL}{GPL}]{\textsl  {General Public License}}
\newacro{GPL}[\AC@hyperlink{GPL}{GPL}]{\textsl  {General Public License}}
\newacro{UTN-FRC}[\AC@hyperlink{UTN-FRC}{UTN-FRC}]{Universidad Tecnol\IeC {\'o}gica Nacional -- Facultad Regional C\IeC {\'o}rdoba}
\newacro{UTN-FRC}[\AC@hyperlink{UTN-FRC}{UTN-FRC}]{Universidad Tecnol\IeC {\'o}gica Nacional -- Facultad Regional C\IeC {\'o}rdoba}
\@writefile{toc}{\contentsline {section}{\numberline {B}Repositorio de proyecto}{13}}
\@writefile{toc}{\contentsline {section}{\numberline {B}Repositorio de proyecto}{14}}
\@writefile{toc}{\contentsline {section}{\numberline {B}Repositorio de proyecto}{14}}
\@writefile{toc}{\contentsline {section}{\numberline {B}Repositorio de proyecto}{14}}

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