| Line 4... |
Line 4... |
\usepackage [utf8] {inputenc}
|
\usepackage [utf8] {inputenc}
|
\usepackage [spanish] {babel}
|
\usepackage [spanish] {babel}
|
\usepackage{multirow}
|
\usepackage{multirow}
|
\usepackage{multicol}
|
\usepackage{multicol}
|
\usepackage{graphicx}
|
\usepackage{graphicx}
|
|
%\usepackage[hyphens]{url}
|
|
%\usepackage[hyphenbreaks]{breakurl}
|
|
\usepackage{url}
|
\usepackage[hyphenbreaks]{breakurl}
|
\usepackage[hyphenbreaks]{breakurl}
|
\usepackage[hyphens]{url}
|
|
|
|
% \usepackage{comment}
|
|
% \excludecomment{figure}
|
|
|
|
\graphicspath{{images/}}
|
\graphicspath{{images/}}
|
%\graphicspath{{images/images-from-uEA2014/}}
|
%\graphicspath{{images/images-from-uEA2014/}}
|
|
|
%\setbeamertemplate{navigation symbols}{} % borra los controles de navegación
|
%\setbeamertemplate{navigation symbols}{} % borra los controles de navegación
|
| Line 253... |
Line 252... |
\end{center}
|
\end{center}
|
\end{frame}
|
\end{frame}
|
|
|
\section{Antecedentes} %%%%%%%%%%%%%%%%
|
\section{Antecedentes} %%%%%%%%%%%%%%%%
|
|
|
|
\subsection[Placa CPLD]{Kit de Desarrollo Educativo con CPLD}
|
|
|
\begin{frame}
|
\begin{frame}
|
\frametitle{Kit de Desarrollo educativo con CPLD}
|
\frametitle{Kit de Desarrollo educativo con CPLD}
|
\begin{center}
|
\begin{center}
|
\includegraphics<1>[width=0.9\textwidth]{images-from-uEA2014/block1cpld}
|
\includegraphics<1>[width=0.9\textwidth]{images-from-uEA2014/block1cpld}
|
\includegraphics<2>[width=0.9\textwidth]{images-from-uEA2014/block2cpld}
|
\includegraphics<2>[width=0.9\textwidth]{images-from-uEA2014/block2cpld}
|
| Line 269... |
Line 270... |
\includegraphics[height=0.5\textheight]{images-from-uEA2014/kit_cpld_per.png} \hspace{1ex}
|
\includegraphics[height=0.5\textheight]{images-from-uEA2014/kit_cpld_per.png} \hspace{1ex}
|
\includegraphics[height=0.4\textheight]{images-from-uEA2014/kit_cpld.png}
|
\includegraphics[height=0.4\textheight]{images-from-uEA2014/kit_cpld.png}
|
\end{center}
|
\end{center}
|
\end{frame}
|
\end{frame}
|
|
|
|
\subsection{Proyecto FPGALibre}
|
|
|
\begin{frame}
|
\begin{frame}
|
\frametitle{FPGALibre.sourceforge.net}
|
\frametitle{FPGALibre.sourceforge.net}
|
\begin{center}
|
\begin{center}
|
\includegraphics[width=\textwidth]{images-from-uEA2014/fpgalibreweb}
|
\includegraphics[width=\textwidth]{images-from-uEA2014/fpgalibreweb}
|
\end{center}
|
\end{center}
|
| Line 290... |
Line 293... |
necesarios para el desarrollo con
|
necesarios para el desarrollo con
|
FPGA. Ambos proyectos iniciados
|
FPGA. Ambos proyectos iniciados
|
por INTI – Electrónica e Informática.
|
por INTI – Electrónica e Informática.
|
Toda la información de la tarjeta
|
Toda la información de la tarjeta
|
S3PROTO-MINI se encuentra en el
|
S3PROTO-MINI se encuentra en el
|
sitio del proyecto FPGALibre
|
sitio del proyecto FPGALibre\cite{s3proto-mini}.
|
\end{block}
|
\end{block}
|
|
|
\begin{block}{Proyecto S3PROTO}
|
% \begin{block}{Proyecto S3PROTO}
|
El proyecto S3PROTO tiene como
|
% El proyecto S3PROTO tiene como
|
objetivo final crear una plataforma
|
% objetivo final crear una plataforma
|
FPGA que pueda alojar un diseño
|
% FPGA que pueda alojar un diseño
|
con un procesador LEON3 (GRLib) y
|
% con un procesador LEON3 (GRLib) y
|
un sistema GNU/Linux embebido.
|
% un sistema GNU/Linux embebido.
|
Para lograr esto es necesario
|
% Para lograr esto es necesario
|
primero abordar diseños multicapas y
|
% primero abordar diseños multicapas y
|
con chips FPGA de encapsulado
|
% con chips FPGA de encapsulado
|
BGA. Con este propósito se realizó el
|
% BGA. Con este propósito se realizó el
|
diseño de la S3PROTO-MIN
|
% diseño de la S3PROTO-MIN
|
\end{block}
|
% \end{block}
|
|
|
\end{center}
|
\end{center}
|
\end{frame}
|
\end{frame}
|
|
|
\begin{frame}
|
\begin{frame}
|
| Line 388... |
Line 391... |
\end{column}
|
\end{column}
|
|
|
\end{columns}
|
\end{columns}
|
\end{frame}
|
\end{frame}
|
|
|
|
% \begin{frame}
|
|
% \frametitle{Plataforma de Hardware Reconfigurable}
|
|
% \begin{center}
|
|
% \includegraphics[width=1\textwidth]{images-from-uEA2014/phr_small.png}
|
|
% \end{center}
|
|
% \end{frame}
|
|
|
|
% \begin{frame}
|
|
% \frametitle{Hardware libre}
|
|
% \begin{center}
|
|
% \includegraphics[width=0.9\textwidth]{images-from-uEA2014/Ohw-logo.pdf}
|
|
% \end{center}
|
|
% \end{frame}
|
|
|
|
|
|
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
\section{Placa PHR}
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
|
\begin{frame}
|
\begin{frame}
|
\frametitle{Plataforma de Hardware Reconfigurable}
|
\frametitle{Placa PHR}
|
\begin{center}
|
\begin{center}
|
\includegraphics[width=1\textwidth]{images-from-uEA2014/phr_small.png}
|
\includegraphics[width=\textwidth]{images-from-uEA2014/phr_text.png}
|
\end{center}
|
\end{center}
|
\end{frame}
|
\end{frame}
|
|
|
\begin{frame}
|
\begin{frame}
|
\frametitle{Hardware libre}
|
\frametitle{Diagrama de bloques del Hardware}
|
|
%\transfade
|
\begin{center}
|
\begin{center}
|
\includegraphics[width=0.9\textwidth]{images-from-uEA2014/Ohw-logo.pdf}
|
\includegraphics<1>[width=0.9\textwidth]{images-from-uEA2014/block1.pdf}
|
|
\includegraphics<2>[width=0.9\textwidth]{images-from-uEA2014/block2.pdf}
|
|
\includegraphics<3>[width=0.9\textwidth]{images-from-uEA2014/block3.pdf}
|
\end{center}
|
\end{center}
|
\end{frame}
|
\end{frame}
|
|
|
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
\section[Dispositivos]{Dispositivos Principales}
|
\subsection[Dispositivos]{Dispositivos Principales}
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
|
\subsection{FPGA} %%%%%%%%%%%%%%%%%%%%%%%%%%%
|
\subsubsection{FPGA} %%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
|
\begin{frame}
|
\begin{frame}
|
\frametitle{FPGA}
|
\frametitle{FPGA}
|
\begin{center}
|
\begin{center}
|
\only<1-2>{
|
\only<1-2>{
|
| Line 462... |
Line 487... |
\end{tabular}
|
\end{tabular}
|
}
|
}
|
\end{center}
|
\end{center}
|
\end{frame}
|
\end{frame}
|
|
|
\subsection{Memoria de Configuración} %%%%%%%%%%%%%%%%%%%%%%%%%%%
|
\subsubsection{Memoria de Configuración} %%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
|
\begin{frame}
|
\begin{frame}
|
\frametitle{Tipo de memoria para la familia Spartan-3A}
|
\frametitle{Tipo de memoria para la familia Spartan-3A}
|
\begin{center}
|
\begin{center}
|
\only<1-2>{
|
\only<1-2>{
|
| Line 488... |
Line 513... |
\end{tabular}
|
\end{tabular}
|
}
|
}
|
\end{center}
|
\end{center}
|
\end{frame}
|
\end{frame}
|
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
\section{Placa PHR}
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
|
|
\begin{frame}
|
|
\frametitle{Placa PHR}
|
|
\begin{center}
|
|
\includegraphics[width=\textwidth]{images-from-uEA2014/phr_text.png}
|
|
\end{center}
|
|
\end{frame}
|
|
|
|
\begin{frame}
|
|
\frametitle{Diagrama de bloques del Hardware}
|
|
%\transfade
|
|
\begin{center}
|
|
\includegraphics<1>[width=0.9\textwidth]{images-from-uEA2014/block1.pdf}
|
|
\includegraphics<2>[width=0.9\textwidth]{images-from-uEA2014/block2.pdf}
|
|
\includegraphics<3>[width=0.9\textwidth]{images-from-uEA2014/block3.pdf}
|
|
\end{center}
|
|
\end{frame}
|
|
|
|
\subsection{Características} %%%%%%%%%%%%%%%%%%%%%%%%%%%
|
\subsection{Características} %%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
|
\begin{frame}
|
\begin{frame}
|
\frametitle{Características}
|
\frametitle{Características}
|
|
|
| Line 536... |
Line 540... |
\item [GPIO:] 28 pines en total
|
\item [GPIO:] 28 pines en total
|
\end{description}
|
\end{description}
|
|
|
\end{frame}
|
\end{frame}
|
|
|
\begin{frame}
|
% \begin{frame}
|
\frametitle{El chip FPGA (XC3S200A)}
|
% \frametitle{El chip FPGA (XC3S200A)}
|
\begin{description}[E/S pares diferenciales máximo:]
|
% \begin{description}[E/S pares diferenciales máximo:]
|
\item [Número de compuertas:] 200K
|
% \item [Número de compuertas:] 200K
|
\item [Celdas lógicas equivalentes:] 4032
|
% \item [Celdas lógicas equivalentes:] 4032
|
\item [CLBs:] 448
|
% \item [CLBs:] 448
|
\item [Bits de RAM distribuida:] 28K
|
% \item [Bits de RAM distribuida:] 28K
|
\item [Bits de Bloques de RAM:] 288K
|
% \item [Bits de Bloques de RAM:] 288K
|
\item [Multiplicadores dedicados:] 16
|
% \item [Multiplicadores dedicados:] 16
|
\item [DCMs:] 4
|
% \item [DCMs:] 4
|
\item [Máximo número de E/S:] 248
|
% \item [Máximo número de E/S:] 248
|
\item [E/S pares diferenciales máximo:] 112
|
% \item [E/S pares diferenciales máximo:] 112
|
\end{description}
|
% \end{description}
|
\end{frame}
|
% \end{frame}
|
|
|
|
|
\begin{frame}[b]
|
\begin{frame}[b]
|
\frametitle{Periféricos}
|
\frametitle{Periféricos}
|
\only<1-5>{
|
\only<1-5>{
|
| Line 667... |
Line 671... |
\item<3-> Arranque suave e independiente para cada regulador.
|
\item<3-> Arranque suave e independiente para cada regulador.
|
\item<4-> Tensiones ajustables de 1.2 V a 6.5 V para los convertidores Buck y de 1.0 V a 6.5 V para el convertidor lineal.
|
\item<4-> Tensiones ajustables de 1.2 V a 6.5 V para los convertidores Buck y de 1.0 V a 6.5 V para el convertidor lineal.
|
\end{itemize}
|
\end{itemize}
|
\end{frame}
|
\end{frame}
|
|
|
\begin{frame}
|
% \begin{frame}
|
\frametitle{Arranque}
|
% \frametitle{Arranque}
|
\begin{center}
|
% \begin{center}
|
\includegraphics[width=0.9\textwidth]{images-from-uEA2014/arranque.pdf}
|
% \includegraphics[width=0.9\textwidth]{images-from-uEA2014/arranque.pdf}
|
\end{center}
|
% \end{center}
|
\end{frame}
|
% \end{frame}
|
|
|
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
\section{Placa OOCDLink}
|
\section{Placa OOCDLink}
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| Line 827... |
Line 831... |
\end{frame}
|
\end{frame}
|
|
|
\appendix
|
\appendix
|
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
\section*{Terminando}
|
\section*{OpenHardware}
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
|
|
\subsection{Comunidad} %%%%%%%%%%%%%%%%
|
\subsection{Comunidad} %%%%%%%%%%%%%%%%
|
|
|
\begin{frame}
|
\begin{frame}
|
| Line 924... |
Line 928... |
|
|
\beamertemplatebookbibitems
|
\beamertemplatebookbibitems
|
\bibitem{act-curricula}
|
\bibitem{act-curricula}
|
P.~Cayuela, \emph{Actualización de la currícula -- Incorporación de la lógica programable en ingeniería}, Jornada de Investigación y Desarrollo en Ingeniería de Software (JIDIS'07). Córdoba Argentina. 2007.
|
P.~Cayuela, \emph{Actualización de la currícula -- Incorporación de la lógica programable en ingeniería}, Jornada de Investigación y Desarrollo en Ingeniería de Software (JIDIS'07). Córdoba Argentina. 2007.
|
|
|
|
\beamertemplatebookbibitems
|
|
\bibitem{s3proto-mini}
|
|
FPGALibre, \emph{S3PROTO-MINI - Proyecto FPGA Libre - SourceForge}, url: \texttt{\burl{http://fpgalibre.sourceforge.net/varios/brochure-s3proto-mini.pdf}}.
|
|
|
\end{thebibliography}
|
\end{thebibliography}
|
\end{frame}
|
\end{frame}
|
|
|
\subsection{Fin} %%%%%%%%%%%%%%%%
|
\subsection{Fin} %%%%%%%%%%%%%%%%
|
|
|
|
% \begin{frame}
|
|
% \frametitle{¿Preguntas?}
|
|
% \begin{center}
|
|
% \includegraphics[height=0.9\textheight]{images-from-uEA2014/question_.pdf}
|
|
% \end{center}
|
|
% \end{frame}
|
|
|
\begin{frame}
|
\begin{frame}
|
\frametitle{¿Preguntas?}
|
\frametitle{Fin}
|
\begin{center}
|
\begin{center}
|
\includegraphics[height=0.9\textheight]{images-from-uEA2014/question_.pdf}
|
¡Muchas gracias!\\
|
|
¿Preguntas?
|
\end{center}
|
\end{center}
|
\end{frame}
|
\end{frame}
|
|
|
|
|
\end{document}
|
\end{document}
|
|
|
No newline at end of file
|
No newline at end of file
|
