URL https://opencores.org/ocsvn/phr/phr/trunk

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[/] [phr/] [trunk/] [placas/] [OT-CPLD-rev2/] [cpld.bak] - Diff between revs 346 and 347

Rev 346	Rev 347
Line 1...	Line 1...
`EESchema Schematic File Version 2 date jue 26 jun 2014 23:07:26 ART`	`EESchema Schematic File Version 2 date vie 27 jun 2014 17:28:40 ART`
`LIBS:power`	`LIBS:power`
`LIBS:device`	`LIBS:device`
`LIBS:transistors`	`LIBS:transistors`
`LIBS:conn`	`LIBS:conn`
`LIBS:linear`	`LIBS:linear`
Line 326...	Line 326...
`F 0 "P1" V 2500 2700 60 0000 C CNN`	`F 0 "P1" V 2500 2700 60 0000 C CNN`
`F 1 "CONN_20-CPLD" V 2600 2700 60 0000 C CNN`	`F 1 "CONN_20-CPLD" V 2600 2700 60 0000 C CNN`
`1 2550 2700`	`1 2550 2700`
`1 0 0 -1`	`1 0 0 -1`
`$EndComp`	`$EndComp`
`Text Label 8050 1350 0 60 ~ 0`	`Text Label 9000 1350 0 60 ~ 0`
`VCC`	`VCC`
`Text Label 4300 5800 0 60 ~ 0`	`Text Label 4300 5800 0 60 ~ 0`
`VCCEXT`	`VCCEXT`
`$Comp`	`$Comp`
`L GND #PWR01`	`L GND #PWR01`
Line 671...	Line 671...
`GND`	`GND`
`Text Label 3650 1750 0 60 ~ 0`	`Text Label 3650 1750 0 60 ~ 0`
`VCC`	`VCC`
`Text Label 1900 1750 0 60 ~ 0`	`Text Label 1900 1750 0 60 ~ 0`
`Vpower`	`Vpower`
`Text Label 9000 1350 0 60 ~ 0`	`Text Label 8050 1350 0 60 ~ 0`
`VCC33`	`VCC33`
`$Comp`	`$Comp`
`L GND #PWR07`	`L GND #PWR07`
`U 1 1 4EA65469`	`U 1 1 4EA65469`
`P 3200 6750`	`P 3200 6750`