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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Testbench for the UNFFT64_core - FFT 64 processor ////
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//// ////
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//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
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//// Company: Unicore Systems http://unicore.co.ua ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2006-2010 Unicore Systems LTD ////
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//// www.unicore.co.ua ////
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//// o.uzenkov@unicore.co.ua ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED "AS IS" ////
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//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
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//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
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//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
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//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
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//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
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//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
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//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
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//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
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//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
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//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
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//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
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//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
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//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// FUNCTION:a set of 4 sine waves is inputted to the FFT processor,
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// the results are compared with the expected waves,
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// the square root mean error is calculated (without a root)
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// FILES: USFFT64_2B_TB.v - this file, contains
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// USFFT64_2B.v - unit under test
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// sin_tst_rom.v - rom with the test waveform, generating by
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// sinerom64_gen.pl
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// PROPERTIES: 1) the calculated error after ca. 4us modeling
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// is outputted to the console as the note:
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// rms error is 1 lsb
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// 2)if the error is 0,1,2 then the test is OK
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// 3) the customer can exchange the test selecting the
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// different frequencies and generating the wave ROM by
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// the script sinerom64_gen.pl
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// 4) the proper operation can be checked by investigation
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// of the core output waveforms
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/////////////////////////////////////////////////////////////////////
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`include "FFT64_CONFIG.inc"
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`timescale 1ns / 1ps
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module USFFT64_2B_tb;
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//Parameters declaration:
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//defparam UUT.nb = 12;
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`USFFT64paramnb
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//Internal signals declarations:
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reg CLK;
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reg RST;
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reg ED;
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reg START;
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reg [3:0]SHIFT;
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wire [nb-1:0]DR;
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wire [nb-1:0]DI;
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wire RDY;
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wire OVF1;
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wire OVF2;
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wire [5:0]ADDR;
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wire signed [nb+2:0]DOR;
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wire signed [nb+2:0]DOI;
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initial
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begin
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CLK = 1'b0;
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forever #5 CLK = ~CLK;
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end
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initial
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begin
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SHIFT = 4'b0000;
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ED = 1'b1;
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RST = 1'b0;
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START = 1'b0;
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#13 RST =1'b1;
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#43 RST =1'b0;
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#53 START =1'b1;
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#12 START =1'b0;
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end
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reg [5:0] ct64;
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always @(posedge CLK or posedge START) begin
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if (START) ct64 = 6'b000000;
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else ct64 = ct64 + 'd1;
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end
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wire [15:0] DATA_RE,DATA_IM,DATA_0;
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Wave_ROM64 UG( .ADDR(ct64) ,
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.DATA_RE(DATA_RE), .DATA_IM(DATA_IM), .DATA_REF(DATA_0) );//
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assign DR=DATA_RE[15:15-nb+1];
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assign DI=DATA_IM[15:15-nb+1];
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// Unit Under Test
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USFFT64_2B UUT (
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.CLK(CLK),
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.RST(RST),
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.ED(ED),
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.START(START),
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.SHIFT(SHIFT),
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.DR(DR),
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.DI(DI),
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.RDY(RDY),
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.OVF1(OVF1),
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.OVF2(OVF2),
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.ADDR(ADDR),
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.DOR(DOR),
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.DOI(DOI));
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wire [5:0] addrr;
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`ifdef USFFT64paramifft
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assign addrr= (64-ADDR); //the result order if IFFT
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`else
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assign addrr= ADDR;
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`endif
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wire signed [15:0] DATA_R0,DATA_I0,DATA_REF;
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Wave_ROM64 UR( .ADDR(addrr) ,
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.DATA_RE(DATA_R0), .DATA_IM(DATA_I0), .DATA_REF(DATA_REF) );//
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wire signed [18:15-nb+1] DREF=2*DATA_REF[15:15-nb+1];
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integer sqra;
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integer ctres;
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reg f;
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initial f=0;
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always@(posedge CLK) begin
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if (f)
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ctres=ctres+1;
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if (RST || RDY) begin
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if (RDY) f=1;
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sqra=0;
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ctres=0; end
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else if (ctres<64) begin
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#2 sqra = sqra +(DREF-DOR)*(DREF-DOR);
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#2 sqra = sqra +(DOI)*(DOI); end
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else if (ctres==64)
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$display("rms error is ", (sqra/128), " lsb");
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end
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endmodule
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No newline at end of file
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