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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ROM with 64 samples of sine waves at the frequencies 0/1 ////
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//// ////
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//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
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//// Company: Unicore Systems http://unicore.co.ua ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2006-2010 Unicore Systems LTD ////
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//// www.unicore.co.ua ////
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//// o.uzenkov@unicore.co.ua ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED "AS IS" ////
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//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
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//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
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//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
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//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
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//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
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//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
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//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
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//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
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//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
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//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
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//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
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//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
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//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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`timescale 1 ns / 1 ps
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module Wave_ROM64 ( ADDR ,DATA );
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output [15:0] DATA ;
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input [5:0] ADDR ;
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reg [15:0] sine[0:63];
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initial begin
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sine[0]=16'h0000; sine[1]=16'h0C8B; sine[2]=16'h18F8; sine[3]=16'h2527;
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sine[4]=16'h30FB; sine[5]=16'h3C56; sine[6]=16'h471C; sine[7]=16'h5133;
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sine[8]=16'h5A82; sine[9]=16'h62F1; sine[10]=16'h6A6D; sine[11]=16'h70E2;
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sine[12]=16'h7641; sine[13]=16'h7A7C; sine[14]=16'h7D8A; sine[15]=16'h7F62;
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sine[16]=16'h7FFF; sine[17]=16'h7F62; sine[18]=16'h7D8A; sine[19]=16'h7A7C;
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sine[20]=16'h7641; sine[21]=16'h70E2; sine[22]=16'h6A6D; sine[23]=16'h62F1;
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sine[24]=16'h5A82; sine[25]=16'h5133; sine[26]=16'h471C; sine[27]=16'h3C56;
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sine[28]=16'h30FB; sine[29]=16'h2527; sine[30]=16'h18F8; sine[31]=16'h0C8B;
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sine[32]=16'h0000; sine[33]=16'hF375; sine[34]=16'hE708; sine[35]=16'hDAD9;
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sine[36]=16'hCF05; sine[37]=16'hC3AA; sine[38]=16'hB8E4; sine[39]=16'hAECD;
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sine[40]=16'hA57E; sine[41]=16'h9D0F; sine[42]=16'h9593; sine[43]=16'h8F1E;
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sine[44]=16'h89BF; sine[45]=16'h8584; sine[46]=16'h8276; sine[47]=16'h809E;
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sine[48]=16'h8001; sine[49]=16'h809E; sine[50]=16'h8276; sine[51]=16'h8584;
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sine[52]=16'h89BF; sine[53]=16'h8F1E; sine[54]=16'h9593; sine[55]=16'h9D0F;
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sine[56]=16'hA57E; sine[57]=16'hAECD; sine[58]=16'hB8E4; sine[59]=16'hC3AA;
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sine[60]=16'hCF05; sine[61]=16'hDAD9; sine[62]=16'hE708; sine[63]=16'hF375;
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end
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assign DATA=sine[ADDR];
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endmodule
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