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/////////////////////////////////////////////////////////////////////
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//// ////
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//// 8-point FFT, First stage of FFT 64 processor ////
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//// ////
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//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
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//// Company: Unicore Systems http://unicore.co.ua ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2006-2010 Unicore Systems LTD ////
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//// www.unicore.co.ua ////
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//// o.uzenkov@unicore.co.ua ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED "AS IS" ////
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//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
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//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
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//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
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//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
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//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
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//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
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//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
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//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
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//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
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//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
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//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
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//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
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//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// Design_Version : 1.0
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// File name : FFT8.v
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// File Revision :
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// Last modification : Sun Sep 30 20:11:56 2007
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/////////////////////////////////////////////////////////////////////
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// FUNCTION: 8-point FFT
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// FILES: FFT8.v - 1-st stage, contains
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// MPU707.v - multiplier to the factor 0.707.
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// PROPERTIES:1) Fully pipelined
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// 2) Each clock cycle complex datum is entered
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// and complex result is outputted
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// 3) Has 8-clock cycle period starting with the START
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// impulse and continuing forever
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// 4) rounding is not used
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// 5)Algorithm is from the book "H.J.Nussbaumer FFT and
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// convolution algorithms".
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// 6)IFFT is performed by substituting the output result
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// order to the reversed one
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// (by exchanging - to + and + to -)
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/////////////////////////////////////////////////////////////////////
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//Algorithm:
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// procedure FFT8(
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// D: in MEMOC8; -- input array
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// DO:out MEMOC8) -- output ARRAY
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// is
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// variable t1,t2,t3,t4,t5,t6,t7,t8,m0,m1,m2,m3,m4,m5,m6,m7: complex;
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// variable s1,s2,s3,s4: complex;
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// begin
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// t1:=D(0) + D(4);
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// m3:=D(0) - D(4);
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// t2:=D(6) + D(2);
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// m6:=CBASE_j*(D(6)-D(2));
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// t3:=D(1) + D(5);
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// t4:=D(1) - D(5);
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// t5:=D(3) + D(7);
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// t6:=D(3) - D(7);
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// t8:=t5 + t3;
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// m5:=CBASE_j*(t5-t3);
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// t7:=t1 + t2;
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// m2:=t1 - t2;
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// m0:=t7 + t8;
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// m1:=t7 - t8;
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// m4:=SQRT(0.5)*(t4 - t6);
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// m7:=-CBASE_j*SQRT(0.5)*(t4 + t6);
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// s1:=m3 + m4;
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// s2:=m3 - m4;
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// s3:=m6 + m7;
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// s4:=m6 - m7;
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// DO(0):=m0;
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// DO(4):=m1;
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// DO(1):=s1 + s3;
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// DO(7):=s1 - s3;
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// DO(2):=m2 + m5;
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// DO(6):=m2 - m5;
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// DO(5):=s2 + s4;
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// DO(3):=s2 - s4;
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// end procedure;
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/////////////////////////////////////////////////////////////////////
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`timescale 1ps / 1ps
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`include "FFT64_CONFIG.inc"
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module FFT8 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY );
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`USFFT64paramnb
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input ED ;
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wire ED ;
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input RST ;
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wire RST ;
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input CLK ;
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wire CLK ;
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input [nb-1:0] DII ;
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wire [nb-1:0] DII ;
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input START ;
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wire START ;
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input [nb-1:0] DIR ;
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wire [nb-1:0] DIR ;
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output [nb+2:0] DOI ;
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wire [nb+2:0] DOI ;
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output [nb+2:0] DOR ;
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wire [nb+2:0] DOR ;
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output RDY ;
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reg RDY ;
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reg [2:0] ct; //main phase counter
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reg [3:0] ctd; //delay counter
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always @( posedge CLK) begin //Control counter
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//
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if (RST) begin
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ct<=0;
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ctd<=15;
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RDY<=0; end
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else if (START) begin
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ct<=0;
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ctd<=0;
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RDY<=0; end
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else if (ED) begin
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RDY<=0;
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ct<=ct+1;
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if (ctd !=4'b1111)
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ctd<=ctd+1;
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if (ctd==12 )
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RDY<=1;
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end
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end
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reg signed [nb-1: 0] dr,d1r,d2r,d3r,d4r,di,d1i,d2i,d3i,d4i;
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always @(posedge CLK) // input register file
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begin
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if (ED) begin
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dr<=DIR;
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d1r<=dr;
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d2r<=d1r;
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d3r<=d2r;
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d4r<=d3r;
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di<=DII;
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d1i<=di;
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d2i<=d1i;
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d3i<=d2i;
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d4i<=d3i;
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end
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end
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reg signed [nb:0] s1r,s2r,s1d1r,s1d2r,s1d3r,s2d1r,s2d2r,s2d3r;
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reg signed [nb:0] s1i,s2i,s1d1i,s1d2i,s1d3i,s2d1i,s2d2i,s2d3i;
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always @(posedge CLK) begin // S1,S2 =t1-t6,m3 and delayed
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if (ED && ((ct==5) || (ct==6) || (ct==7) || (ct==0))) begin
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s1r<=d4r + dr ;
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s1i<=d4i + di ;
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s2r<=d4r - dr ;
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s2i<= d4i - di;
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end
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if (ED) begin
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s1d1r<=s1r;
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s1d2r<=s1d1r;
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s1d1i<=s1i;
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s1d2i<=s1d1i;
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if (ct==0 || ct==1) begin //## note for vhdl
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s1d3r<=s1d2r;
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s1d3i<=s1d2i;
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end
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if (ct==6 || ct==7 || ct==0) begin
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s2d1r<=s2r;
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s2d2r<=s2d1r;
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s2d1i<=s2i;
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s2d2i<=s2d1i;
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end
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if (ct==0) begin
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s2d3r<=s2d2r;
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s2d3i<=s2d2i;
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end
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end
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end
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reg signed [nb+1:0] s3r,s4r,s3d1r,s3d2r,s3d3r;
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reg signed [nb+1:0] s3i,s4i,s3d1i,s3d2i,s3d3i;
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always @(posedge CLK) begin //ALU S3:
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if (ED)
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case (ct)
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0: begin s3r<= s1d2r+s1r; //t7
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s3i<= s1d2i+ s1i ;end
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1: begin s3r<= s1d3r - s1d1r; //m2
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s3i<= s1d3i - s1d1i; end
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2: begin s3r<= s1d3r +s1r; //t8
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s3i<= s1d3i+ s1i ; end
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3: begin s3r<= s1d3r - s1r; //
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s3i<= s1d3i - s1i ; end
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endcase
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if (ED) begin
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if (ct==1 || ct==2 || ct==3) begin
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s3d1r<=s3r; //t8
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s3d1i<=s3i;
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end
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if ( ct==2 || ct==3) begin
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s3d2r<=s3d1r; //m2
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s3d3r<=s3d2r; //t7
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s3d2i<=s3d1i;
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s3d3i<=s3d2i;
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end
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end
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end
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always @ (posedge CLK) begin // S4
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if (ED) begin
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if (ct==1) begin
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s4r<= s2d2r + s2r;
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s4i<= s2d2i + s2i; end
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else if (ct==2) begin
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s4r<=s2d2r - s2r;
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s4i<= s2d2i - s2i;
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end
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end
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end
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assign em = ((ct==2 || ct==3 || ct==4)&& ED);
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wire signed [nb+1:0] m4m7r,m4m7i;
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MPU707 #(nb) UMR( .CLK(CLK),.EI(em),.DI(s4r),.DO(m4m7r)); // UMR
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MPU707 #(nb) UMI( .CLK(CLK),.EI(em),.DI(s4i), .DO(m4m7i)); // UMR
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reg signed [nb+1:0] sjr,sji, m6r,m6i;
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always @ (posedge CLK) begin //multiply by J
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if (ED) begin
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case (ct)
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3: begin sjr<= s2d1i; //m6
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sji<=0 - s2d1r; end
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4: begin sjr<= m4m7i; //m7
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sji<=0 - m4m7r;end
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6: begin sjr<= s3i; //m5
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sji<=0 - s3r; end
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endcase
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if (ct==4) begin
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m6r<=sjr; //m6
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m6i<=sji;
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end
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end
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end
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reg signed [nb+2:0] s5r,s5d1r,s5d2r,q1r;
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reg signed [nb+2:0] s5i,s5d1i,s5d2i,q1i;
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always @ (posedge CLK) // S5:
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if (ED)
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case (ct)
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5: begin q1r<=s2d3r +m4m7r ; // S1
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q1i<=s2d3i +m4m7i ;
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s5r<=m6r + sjr;
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s5i<=m6i + sji; end
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6: begin s5r<=m6r - sjr;
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s5i<=m6i - sji;
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s5d1r<=s5r;
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s5d1i<=s5i; end
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7: begin s5r<=s2d3r - m4m7r;
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s5i<=s2d3i - m4m7i;
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s5d1r<=s5r;
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s5d1i<=s5i;
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s5d2r<=s5d1r;
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s5d2i<=s5d1i;
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end
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endcase
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reg signed [nb+3:0] s6r,s6i ;
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`ifdef paramifft
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always @ (posedge CLK) begin // S6-- result adder
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if (ED)
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case (ct)
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5: begin s6r<=s3d3r +s3d1r ; // -- D0
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s6i<=s3d3i +s3d1i ;end //-- D0
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6: begin
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s6r<=q1r - s5r ;
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s6i<=q1i - s5i ; end
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7: begin
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s6r<=s3d2r - sjr ;
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s6i<=s3d2i - sji ; end
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0: begin
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s6r<=s5r + s5d1r ;
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s6i<= s5i +s5d1i ; end
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1:begin s6r<=s3d3r - s3d1r ; //-- D4
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s6i<=s3d3i - s3d1i ; end
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2: begin
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s6r<= s5r - s5d1r ; // D5
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s6i<= s5i - s5d1i ; end
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3: begin // D6
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s6r<=s3d3r + sjr ;
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s6i<=s3d3i + sji ;
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end
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4: begin // D0
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s6r<= q1r + s5d2r ;
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s6i<= q1i + s5d2i ;
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end
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endcase
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end
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`else
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always @ (posedge CLK) begin // S6-- result adder
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if (ED)
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case (ct)
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5: begin s6r<=s3d3r +s3d1r ; // -- D0
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s6i<=s3d3i +s3d1i ;end //-- D0
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6: begin
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s6r<=q1r + s5r ; //-- D1
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s6i<=q1i + s5i ; end
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7: begin
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s6r<=s3d2r +sjr ; //-- D2
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s6i<=s3d2i +sji ; end
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0: begin
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s6r<=s5r - s5d1r ; // -- D3
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s6i<= s5i - s5d1i ;end
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1:begin s6r<=s3d3r - s3d1r ; //-- D4
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s6i<=s3d3i - s3d1i ; end
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2: begin
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s6r<=s5r + s5d1r ; //-- D5
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s6i<=s5i + s5d1i ; end
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3: begin
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s6r<= s3d3r - sjr ; // D6
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s6i<=s3d3i - sji ; end
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4: begin
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s6r<= q1r - s5d2r ; // D0
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s6i<= q1i - s5d2i ; end
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endcase
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end
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`endif
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assign #1 DOR=s6r[nb+2:0];
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assign #1 DOI= s6i[nb+2:0];
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endmodule
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