Subversion Repositories pipelined_fft_64

/////////////////////////////////////////////////////////////////////

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////  rotating unit, stays between 2 stages of FFT pipeline      ////

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////  Authors: Anatoliy Sergienko, Volodya Lepeha                ////

////  Company: Unicore Systems http://unicore.co.ua              ////

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////  Downloaded from: http://www.opencores.org                  ////

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//// Copyright (C) 2006-2010 Unicore Systems LTD                 ////

//// www.unicore.co.ua                                           ////

//// o.uzenkov@unicore.co.ua                                     ////

////                                                             ////

//// This source file may be used and distributed without        ////

//// restriction provided that this copyright statement is not   ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer.////

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//// THIS SOFTWARE IS PROVIDED "AS IS"                           ////

//// AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ////

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//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ////

//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ////

//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ////

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//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ////

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// Design_Version       : 1.0

// File name            : 

// File Revision        : 

// Last modification    : Sun Sep 30 20:11:56 2007

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// FUNCTION: complex multiplication to the twiddle factors proper to the 64  point FFT

// PROPERTIES: 1) Has 64-clock cycle period starting with the START impulse and continuing forever

//               2) rounding    is not used

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`timescale 1ps / 1ps

`include "FFT64_CONFIG.inc"

module ROTATOR64 (CLK ,RST,ED,START, DR,DI, DOR, DOI,RDY  );

        `USFFT64paramnb

        `USFFT64paramnw

        input RST ;

        wire RST ;

        input CLK ;

        wire CLK ;

        input ED ; //operation enable

        input [nb+1:0] DI;  //Imaginary part of data

        wire [nb+1:0]  DI ;

        input [nb+1:0]  DR ; //Real part of data

        input START ;              //1-st Data is entered after this impulse 

        wire START ;

        output [nb+1:0]  DOI ; //Imaginary part of data

        wire [nb+1:0]  DOI ;

        output [nb+1:0]  DOR ; //Real part of data

        wire [nb+1:0]  DOR ;

        output RDY ;       //repeats START impulse following the output data

        reg RDY ;

        reg [5:0] addrw;

        reg sd1,sd2;

        always  @( posedge CLK)   //address counter for twiddle factors

                begin

                        if (RST) begin

                                        addrw<=0;

                                        sd1<=0;

                                        sd2<=0;

                                end

                        else if (START && ED)  begin

                                        addrw[5:0]<=0;

                                        sd1<=START;

                                        sd2<=0;

                                end

                        else if (ED)      begin

                                        addrw<=addrw+1;

                                        sd1<=START;

                                        sd2<=sd1;

                                        RDY<=sd2;

                                end

                end

                wire signed [nw-1:0] wr,wi; //twiddle factor coefficients

        //twiddle factor ROM

        WROM64 UROM( .ADDR(addrw),      .WR(wr),.WI(wi) );

        reg signed [nb+1 : 0] drd,did;

        reg signed [nw-1 : 0] wrd,wid;

        wire signed [nw+nb+1 : 0] drri,drii,diri,diii;

        reg signed [nb+2:0] drr,dri,dir,dii,dwr,dwi;

        assign          drri=drd*wrd;

        assign  diri=did*wrd;

        assign  drii=drd*wid;

        assign  diii=did*wid;

        always @(posedge CLK)    //complex multiplier    

                begin

                        if (ED) begin

                                        drd<=DR;

                                        did<=DI;

                                        wrd<=wr;

                                        wid<=wi;

                                        drr<=drri[nw+nb+1 :nw-1]; //msbs of multiplications are stored

                                        dri<=drii[nw+nb+1 : nw-1];

                                        dir<=diri[nw+nb+1 : nw-1];

                                        dii<=diii[nw+nb+1 : nw-1];

                                        dwr<=drr - dii;

                                        dwi<=dri + dir;

                                end

                end

        assign DOR=dwr[nb+2:1];

        assign DOI=dwi[nb+2 :1];

endmodule