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/////////////////////////////////////////////////////////////////////
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//// ////
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//// rotating unit, stays between 2 stages of FFT pipeline ////
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//// ////
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//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
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//// Company: Unicore Systems http://unicore.co.ua ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2006-2010 Unicore Systems LTD ////
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//// www.unicore.co.ua ////
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//// o.uzenkov@unicore.co.ua ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED "AS IS" ////
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//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
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//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
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//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
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//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
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//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
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//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
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//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
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//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
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//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
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//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
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//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
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//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
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//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// Design_Version : 1.0
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// File name :
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// File Revision :
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// Last modification : Sun Sep 30 20:11:56 2007
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/////////////////////////////////////////////////////////////////////
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// FUNCTION: complex multiplication to the twiddle factors proper to the 64 point FFT
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// PROPERTIES: 1) Has 64-clock cycle period starting with the START impulse and continuing forever
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// 2) rounding is not used
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/////////////////////////////////////////////////////////////////////
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`timescale 1ps / 1ps
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`include "FFT64_CONFIG.inc"
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module ROTATOR64 (CLK ,RST,ED,START, DR,DI, DOR, DOI,RDY );
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`USFFT64paramnb
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`USFFT64paramnw
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input RST ;
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wire RST ;
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input CLK ;
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wire CLK ;
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input ED ; //operation enable
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input [nb+1:0] DI; //Imaginary part of data
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wire [nb+1:0] DI ;
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input [nb+1:0] DR ; //Real part of data
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input START ; //1-st Data is entered after this impulse
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wire START ;
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output [nb+1:0] DOI ; //Imaginary part of data
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wire [nb+1:0] DOI ;
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output [nb+1:0] DOR ; //Real part of data
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wire [nb+1:0] DOR ;
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output RDY ; //repeats START impulse following the output data
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reg RDY ;
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reg [5:0] addrw;
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reg sd1,sd2;
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always @( posedge CLK) //address counter for twiddle factors
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begin
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if (RST) begin
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addrw<=0;
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sd1<=0;
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sd2<=0;
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end
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else if (START && ED) begin
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addrw[5:0]<=0;
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sd1<=START;
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sd2<=0;
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end
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else if (ED) begin
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addrw<=addrw+1;
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sd1<=START;
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sd2<=sd1;
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RDY<=sd2;
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end
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end
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wire signed [nw-1:0] wr,wi; //twiddle factor coefficients
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//twiddle factor ROM
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WROM64 UROM( .ADDR(addrw), .WR(wr),.WI(wi) );
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reg signed [nb+1 : 0] drd,did;
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reg signed [nw-1 : 0] wrd,wid;
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wire signed [nw+nb+1 : 0] drri,drii,diri,diii;
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reg signed [nb+2:0] drr,dri,dir,dii,dwr,dwi;
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assign drri=drd*wrd;
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assign diri=did*wrd;
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assign drii=drd*wid;
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assign diii=did*wid;
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always @(posedge CLK) //complex multiplier
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begin
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if (ED) begin
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drd<=DR;
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did<=DI;
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wrd<=wr;
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wid<=wi;
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drr<=drri[nw+nb+1 :nw-1]; //msbs of multiplications are stored
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dri<=drii[nw+nb+1 : nw-1];
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dir<=diri[nw+nb+1 : nw-1];
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dii<=diii[nw+nb+1 : nw-1];
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dwr<=drr - dii;
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dwi<=dri + dir;
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end
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end
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assign DOR=dwr[nb+2:1];
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assign DOI=dwi[nb+2 :1];
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endmodule
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