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///////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////                                                               ////
 
////  WISHBONE rev.B2 Wishbone Master model                        ////
 
////                                                               ////
 
////                                                               ////
 
////  Author: Richard Herveille                                    ////
 
////          richard@asics.ws                                     ////
 
////          www.asics.ws                                         ////
 
////                                                               ////
 
////  Downloaded from: http://www.opencores.org/projects/mem_ctrl  ////
 
////                                                               ////
 
///////////////////////////////////////////////////////////////////////
 
////                                                               ////
 
//// Copyright (C) 2001 Richard Herveille                          ////
 
////                    richard@asics.ws                           ////
 
////                                                               ////
 
//// This source file may be used and distributed without          ////
 
//// restriction provided that this copyright statement is not     ////
 
//// removed from the file and that any derivative work contains   ////
 
//// the original copyright notice and the associated disclaimer.  ////
 
////                                                               ////
 
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY       ////
 
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     ////
 
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS     ////
 
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR        ////
 
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,           ////
 
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES      ////
 
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     ////
 
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR          ////
 
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    ////
 
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT    ////
 
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    ////
 
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
 
//// POSSIBILITY OF SUCH DAMAGE.                                   ////
 
////                                                               ////
 
///////////////////////////////////////////////////////////////////////
 
 
 
//  CVS Log
 
//
 
//  $Id: wb_master_model.v,v 1.4 2004/02/28 15:40:42 rherveille Exp $
 
//
 
//  $Date: 2004/02/28 15:40:42 $
 
//  $Revision: 1.4 $
 
//  $Author: rherveille $
 
//  $Locker:  $
 
//  $State: Exp $
 
//
//
// Change History:
//  WISHBONE rev.B2 Wishbone Master model
//
//
 
//  Author: Bob Hayes
 
//          rehayes@opencores.org
 
//
 
//  Downloaded from: http://www.opencores.org/projects/pit.....
 
//
 
////////////////////////////////////////////////////////////////////////////////
 
// Copyright (c) 2011, Robert Hayes
 
//
 
// All rights reserved.
 
//
 
// Redistribution and use in source and binary forms, with or without
 
// modification, are permitted provided that the following conditions are met:
 
//     * Redistributions of source code must retain the above copyright
 
//       notice, this list of conditions and the following disclaimer.
 
//     * Redistributions in binary form must reproduce the above copyright
 
//       notice, this list of conditions and the following disclaimer in the
 
//       documentation and/or other materials provided with the distribution.
 
//     * Neither the name of the  nor the
 
//       names of its contributors may be used to endorse or promote products
 
//       derived from this software without specific prior written permission.
 
//
 
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
 
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
 
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
////////////////////////////////////////////////////////////////////////////////
 
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
 
`include "timescale.v"
`include "timescale.v"
 
 
module wb_master_model  #(parameter dwidth = 32,
module wb_master_model  #(parameter dwidth = 32,
                          parameter awidth = 32)
                          parameter awidth = 32)
(
(
 
  // Wishbone Signals
 
wishbone_if.master           wb_1,          // Define the interface instance name
 
wishbone_if.master           wb_2,          // Define the interface instance name
 
wishbone_if.master           wb_3,          // Define the interface instance name
 
wishbone_if.master           wb_4,          // Define the interface instance name
output logic                 cyc,
output logic                 cyc,
output logic                 stb,
output logic                 stb,
output logic                 we,
output logic                 we,
output logic [dwidth/8 -1:0] sel,
output logic [dwidth/8 -1:0] sel,
output logic [awidth   -1:0] adr,
output logic [awidth   -1:0] adr,
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input  logic                 rst,  // No Connect
input  logic                 rst,  // No Connect
input  logic                 err,  // No Connect
input  logic                 err,  // No Connect
input  logic                 rty   // No Connect
input  logic                 rty   // No Connect
);
);
 
 
////////////////////////////////////////////////////////////////////
//////////////////////////////////
//
//
// Local Wires
// Local Wires
//
//
 
 
 
 
logic [dwidth   -1:0] q;
logic [dwidth   -1:0] q;
 
 
event cmp_error_detect;
event cmp_error_detect;
 
 
////////////////////////////////////////////////////////////////////
assign wb_1.wb_adr = adr[2:0];
 
assign wb_1.wb_sel = 2'b11;
 
assign wb_1.wb_we  = we;
 
assign wb_1.wb_cyc = cyc;
 
assign wb_1.wb_dat = dout;
 
 
 
assign wb_2.wb_adr = adr[2:0];
 
assign wb_2.wb_sel = 2'b11;
 
assign wb_2.wb_we  = we;
 
assign wb_2.wb_cyc = cyc;
 
assign wb_2.wb_dat = dout;
 
 
 
assign wb_3.wb_adr = adr[2:0];
 
assign wb_3.wb_sel = 2'b11;
 
assign wb_3.wb_we  = we;
 
assign wb_3.wb_cyc = cyc;
 
assign wb_3.wb_dat = dout;
 
 
 
assign wb_4.wb_adr = adr[2:0];
 
assign wb_4.wb_sel = 2'b11;
 
assign wb_4.wb_we  = we;
 
assign wb_4.wb_cyc = cyc;
 
assign wb_4.wb_dat = dout[7:0];
 
 
 
//////////////////////////////////
//
//
// Memory Logic
// Memory Logic
//
//
 
 
initial
initial
  begin
  begin
    adr  = 'x;
    adr  <= 'x;
    dout = 'x;
    dout <= 'x;
    cyc  = 1'b0;
    cyc  <= 1'b0;
    stb  = 1'bx;
    stb  <= 1'bx;
    we   = 1'hx;
    we   <= 1'hx;
    sel  = 'x;
    sel  <= 'x;
    #1;
    #1;
    $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");
    $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");
  end
  end
 
 
////////////////////////////////////////////////////////////////////
//////////////////////////////////
//
//
// Wishbone write cycle
// Wishbone write cycle
//
//
 
 
task wb_write(
task wb_write(
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  we   = 1'hx;
  we   = 1'hx;
  sel  = 'x;
  sel  = 'x;
 
 
endtask
endtask
 
 
////////////////////////////////////////////////////////////////////
//////////////////////////////////
//
//
// Wishbone read cycle
// Wishbone read cycle
//
//
 
 
task wb_read(
task wb_read(
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  sel  = 'x;
  sel  = 'x;
  d    = din;
  d    = din;
 
 
endtask
endtask
 
 
////////////////////////////////////////////////////////////////////
//////////////////////////////////
//
//
// Wishbone compare cycle (read data from location and compare with expected data)
// Wishbone compare cycle (read data from location and compare with expected data)
//
//
 
 
task wb_cmp(
task wb_cmp(
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      -> cmp_error_detect;
      -> cmp_error_detect;
      $display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
      $display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
    end
    end
endtask
endtask
 
 
endmodule
endmodule : wb_master_model
 
 
 
 

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