OpenCores
URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 8 and 15

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 8 Rev 15
Line 121... Line 121...
 
 
        // generate clock
        // generate clock
        always #20 mstr_test_clk = ~mstr_test_clk;
        always #20 mstr_test_clk = ~mstr_test_clk;
 
 
        always @(posedge mstr_test_clk)
        always @(posedge mstr_test_clk)
          vector = vector + 1;
          vector <= vector + 1;
 
 
        // hookup wishbone master model
        // hookup wishbone master model
        wb_master_model #(.dwidth(16), .awidth(32))
        wb_master_model #(.dwidth(16), .awidth(32))
                u0 (
                u0 (
                .clk(mstr_test_clk),
                .clk(mstr_test_clk),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.