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[/] [pit/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 8 and 15
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Rev 15 |
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Line 121... |
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// generate clock
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// generate clock
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always #20 mstr_test_clk = ~mstr_test_clk;
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always #20 mstr_test_clk = ~mstr_test_clk;
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always @(posedge mstr_test_clk)
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always @(posedge mstr_test_clk)
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vector = vector + 1;
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vector <= vector + 1;
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// hookup wishbone master model
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// hookup wishbone master model
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wb_master_model #(.dwidth(16), .awidth(32))
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wb_master_model #(.dwidth(16), .awidth(32))
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u0 (
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u0 (
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.clk(mstr_test_clk),
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.clk(mstr_test_clk),
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