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[/] [pit/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 15 and 16

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Rev 15	Rev 16
Line 39...	Line 39...

`include "timescale.v"	`include "timescale.v"

`module tst_bench_top();`	`module tst_bench_top();`

	`parameter STOP_ON_ERROR = 1'b0;`
	`parameter MAX_VECTOR = 1_000;`
`//`	`//`
`// wires && regs`	`// wires && regs`
`//`	`//`
`reg mstr_test_clk;`	`reg mstr_test_clk;`
`reg [19:0] vector;`	`reg [19:0] vector;`
Line 59...	Line 61...
`wire inta_1, inta_2, inta_3, inta_4;`	`wire inta_1, inta_2, inta_3, inta_4;`
`wire count_en_1;`	`wire count_en_1;`
`wire count_flag_1;`	`wire count_flag_1;`

`reg [15:0] q, qq;`	`reg [15:0] q, qq;`
	`reg [15:0] error_count;`

`wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen;`	`wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen;`
`wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen;`	`wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen;`

`// Name Address Locations`	`// Name Address Locations`
Line 101...	Line 104...
`initial`	`initial`
`begin`	`begin`
`mstr_test_clk = 0;`	`mstr_test_clk = 0;`
`vector = 0;`	`vector = 0;`
`test_num = 0;`	`test_num = 0;`
	`error_count = 0;`

`ifdef WAVES	`ifdef WAVES
`$shm_open("waves");`	`$shm_open("waves");`
`$shm_probe("AS",tst_bench_top,"AS");`	`$shm_probe("AS",tst_bench_top,"AS");`
`$display("\nINFO: Signal dump enabled ...\n\n");`	`$display("\nINFO: Signal dump enabled ...\n\n");`
Line 120...	Line 124...
`end`	`end`

`// generate clock`	`// generate clock`
`always #20 mstr_test_clk = ~mstr_test_clk;`	`always #20 mstr_test_clk = ~mstr_test_clk;`

	`// Keep a count of how many clocks we've simulated`
`always @(posedge mstr_test_clk)`	`always @(posedge mstr_test_clk)`
	`begin`
`vector <= vector + 1;`	`vector <= vector + 1;`
	`if (vector > MAX_VECTOR)`
	`begin`
	`error_count <= error_count + 1;`
	`$display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);`
	`wrap_up;`
	`end`
	`end`

	`// Add up errors tha come from WISHBONE read compares`
	`always @u0.cmp_error_detect`
	`begin`
	`error_count <= error_count + 1;`
	`end`

`// hookup wishbone master model`	`// hookup wishbone master model`
`wb_master_model #(.dwidth(16), .awidth(32))`	`wb_master_model #(.dwidth(16), .awidth(32))`
`u0 (`	`u0 (`
`.clk(mstr_test_clk),`	`.clk(mstr_test_clk),`
Line 310...	Line 329...
`mstr_psx_modx(2,4);`	`mstr_psx_modx(2,4);`

`mstr_psx_modx(4,0);`	`mstr_psx_modx(4,0);`

`repeat(100) @(posedge mstr_test_clk);`	`repeat(100) @(posedge mstr_test_clk);`
`$display("\nTestbench done at vector=%d\n", vector);`
`$finish;`	`wrap_up;`
`end`
	`end // Main Test Flow`

`// Poll for flag set`	`// Poll for flag set`
`task wait_flag_set;`	`task wait_flag_set;`
`begin`	`begin`
`u0.wb_read(1, PIT_CNTRL, q);`	`u0.wb_read(1, PIT_CNTRL, q);`
Line 409...	Line 429...
`u0.wb_write(1, PIT_CNTRL, 16'b0); //`	`u0.wb_write(1, PIT_CNTRL, 16'b0); //`

`end`	`end`
`endtask`	`endtask`

	`task wrap_up;`
	`begin`
	`test_num = test_num + 1;`
	`repeat(10) @(posedge mstr_test_clk);`
	`$display("\nSimulation Finished!! - vector =%d", vector);`
	`if (error_count == 0)`
	`$display("Simulation Passed");`
	`else`
	`$display("Simulation Failed --- Errors =%d", error_count);`

	`$finish;`
	`end`
	`endtask`


`endmodule // tst_bench_top`	`endmodule // tst_bench_top`


`No newline at end of file`	`No newline at end of file`

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[/] [pit/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 15 and 16