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[/] [pit/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 16 and 19
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| Rev 16 |
Rev 19 |
| Line 175... |
Line 175... |
({16{stb3}} & {8'b0, dat3_i[7:0]});
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({16{stb3}} & {8'b0, dat3_i[7:0]});
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assign ack = ack_1 || ack_2 || ack_3 || ack_4;
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assign ack = ack_1 || ack_2 || ack_3 || ack_4;
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// hookup wishbone_PIT_master core - Parameters take all default values
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// hookup wishbone_PIT_master core - Parameters take all default values
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// Async Reset, 16 bit Bus, 16 bit Granularity
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// Async Reset, 16 bit Bus, 16 bit Granularity,Wait States
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pit_top pit_1(
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pit_top #(.SINGLE_CYCLE(1'b0))
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pit_1(
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// wishbone interface
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// wishbone interface
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.wb_clk_i(mstr_test_clk),
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.wb_clk_i(mstr_test_clk),
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.wb_rst_i(1'b0),
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.wb_rst_i(1'b0),
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.arst_i(rstn),
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.arst_i(rstn),
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.wb_adr_i(adr[2:0]),
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.wb_adr_i(adr[2:0]),
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