URL https://opencores.org/ocsvn/pit/pit/trunk

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[/] [pit/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Diff between revs 3 and 11

Rev 3	Rev 11
Line 166...	Line 166...

`// wait for acknowledge from slave`	`// wait for acknowledge from slave`
`while(~ack) @(posedge clk);`	`while(~ack) @(posedge clk);`

`// negate wishbone signals`	`// negate wishbone signals`
`#1;`	`d = din; // Grab the data on the posedge of clock`
	`#1; // Delay the clearing (hold time of the control signals`
`cyc = 1'b0;`	`cyc = 1'b0;`
`stb = 1'bx;`	`stb = 1'bx;`
`adr = {awidth{1'bx}};`	`adr = {awidth{1'bx}};`
`dout = {dwidth{1'bx}};`	`dout = {dwidth{1'bx}};`
`we = 1'hx;`	`we = 1'hx;`