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[/] [pit/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Diff between revs 11 and 16
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| Rev 11 |
Rev 16 |
| Line 49... |
Line 49... |
//
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//
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`include "timescale.v"
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`include "timescale.v"
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module wb_master_model #(parameter dwidth = 32,
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module wb_master_model #(parameter dwidth = 32,
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parameter awidth = 32)
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parameter awidth = 32)
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(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
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(
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output reg cyc,
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output reg stb,
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input clk, rst;
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output reg we,
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output [awidth -1:0] adr;
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output reg [dwidth/8 -1:0] sel,
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input [dwidth -1:0] din;
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output reg [awidth -1:0] adr,
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output [dwidth -1:0] dout;
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output reg [dwidth -1:0] dout,
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output cyc, stb;
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input [dwidth -1:0] din,
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output we;
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input clk,
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output [dwidth/8 -1:0] sel;
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input ack,
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input ack, err, rty;
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input rst, // No Connect
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input err, // No Connect
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input rty // No Connect
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);
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Local Wires
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// Local Wires
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//
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//
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reg [awidth -1:0] adr;
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reg [dwidth -1:0] dout;
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reg cyc, stb;
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reg we;
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reg [dwidth/8 -1:0] sel;
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reg [dwidth -1:0] q;
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reg [dwidth -1:0] q;
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event cmp_error_detect;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Memory Logic
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// Memory Logic
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//
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//
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Line 195... |
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begin
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begin
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wb_read (delay, a, q);
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wb_read (delay, a, q);
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if (d_exp !== q)
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if (d_exp !== q)
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begin
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-> cmp_error_detect;
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$display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
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$display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
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end
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end
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end
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endtask
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endtask
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endmodule
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endmodule
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