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[/] [pit/] [trunk/] [rtl/] [sys_verilog/] [pit_count.sv] - Diff between revs 21 and 22

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Rev 21 Rev 22
Line 65... Line 65...
assign rollover = ((cnt_n == mod_value) || no_div) && prescale_out;
assign rollover = ((cnt_n == mod_value) || no_div) && prescale_out;
 
 
assign clear_counter = !counter_sync;
assign clear_counter = !counter_sync;
 
 
//  Div N Counter
//  Div N Counter
always @(posedge bus_clk or negedge async_rst_b)
always_ff @(posedge bus_clk or negedge async_rst_b)
  if ( !async_rst_b )
  if ( !async_rst_b )
    cnt_n  <= 1;
    cnt_n  <= 1;
  else if ( clear_counter || rollover || no_div)
  else if ( clear_counter || rollover || no_div)
    cnt_n  <= 1;
    cnt_n  <= 1;
  else if ( prescale_out )
  else if ( prescale_out )
    cnt_n  <= cnt_n + 1;
    cnt_n  <= cnt_n + 1;
 
 
//  Counter Rollover Flag and Interrupt
//  Counter Rollover Flag and Interrupt
always @(posedge bus_clk or negedge async_rst_b)
always_ff @(posedge bus_clk or negedge async_rst_b)
  if ( !async_rst_b )
  if ( !async_rst_b )
    cnt_flag_o <= 0;
    cnt_flag_o <= 0;
  else if ( clear_counter || pit_flg_clr)
  else if ( clear_counter || pit_flg_clr)
    cnt_flag_o <= 0;
    cnt_flag_o <= 0;
  else if ( rollover )
  else if ( rollover )
    cnt_flag_o <= 1;
    cnt_flag_o <= 1;
 
 
//  PIT Output Register
//  PIT Output Register
always @(posedge bus_clk or negedge async_rst_b)
always_ff @(posedge bus_clk or negedge async_rst_b)
  if ( !async_rst_b )
  if ( !async_rst_b )
    pit_o <= 0;
    pit_o <= 0;
  else
  else
    pit_o <= rollover && counter_sync && !sync_reset;
    pit_o <= rollover && counter_sync && !sync_reset;
 
 

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