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[/] [pit/] [trunk/] [rtl/] [sys_verilog/] [pit_prescale.sv] - Diff between revs 21 and 22
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| Rev 21 |
Rev 22 |
| Line 63... |
Line 63... |
logic rollover; //
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logic rollover; //
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|
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// This was going to be a "generate" block but iverilog does't support that
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// This was going to be a "generate" block but iverilog does't support that
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// command so we'll just have to trust the compiler to simplify the logic based
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// command so we'll just have to trust the compiler to simplify the logic based
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// on the setting of the constant "DECADE_CNTR"
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// on the setting of the constant "DECADE_CNTR"
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always @*
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always_comb
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if ( DECADE_CNTR )
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if ( DECADE_CNTR )
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case (divisor)
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case (divisor)
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0: end_count = 1;
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0: end_count = 1;
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1: end_count = 2;
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1: end_count = 2;
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2: end_count = 4;
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2: end_count = 4;
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| Line 78... |
Line 78... |
7: end_count = 10_000;
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7: end_count = 10_000;
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8: end_count = 20_000;
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8: end_count = 20_000;
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default: end_count = 20_000;
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default: end_count = 20_000;
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endcase
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endcase
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else
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else
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case (divisor)
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unique case (divisor)
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0: end_count = 1;
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0: end_count = 1;
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1: end_count = 2;
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1: end_count = 2;
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2: end_count = 4;
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2: end_count = 4;
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3: end_count = 8;
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3: end_count = 8;
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4: end_count = 16;
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4: end_count = 16;
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| Line 109... |
Line 109... |
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// Div N Counter
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// Div N Counter
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// If the "NO_PRESCALE" parameter is set the compiler should hopefully strip
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// If the "NO_PRESCALE" parameter is set the compiler should hopefully strip
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// these counter bits when the module is compiled because the only place the
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// these counter bits when the module is compiled because the only place the
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// register outputs go to drive a signal "rollover" that is already a constant.
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// register outputs go to drive a signal "rollover" that is already a constant.
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always @(posedge bus_clk or negedge async_rst_b)
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always_ff @(posedge bus_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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cnt_n <= 1;
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cnt_n <= 1;
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else if ( !counter_sync || rollover)
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else if ( !counter_sync || rollover)
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cnt_n <= 1;
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cnt_n <= 1;
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else
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else
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