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[/] [pit/] [trunk/] [rtl/] [sys_verilog/] [pit_regs.sv] - Diff between revs 22 and 24

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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
 
module pit_regs #(parameter ARST_LVL = 1'b0,  // asynchronous reset level
module pit_regs #(parameter COUNT_SIZE = 16,
                  parameter COUNT_SIZE = 16,
 
                  parameter NO_PRESCALE = 1'b0,
                  parameter NO_PRESCALE = 1'b0,
                  parameter DWIDTH = 16)
                  parameter DWIDTH = 16)
  (
  (
  output logic [COUNT_SIZE-1:0] mod_value,    // Main Counter Modulo Value
  output logic [COUNT_SIZE-1:0] mod_value,    // Main Counter Modulo Value
  output                 [ 3:0] pit_pre_scl,  // PIT Prescaler Value
  output                 [ 3:0] pit_pre_scl,  // PIT Prescaler Value
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        cnt_sync_o  <= 1'b0;
        cnt_sync_o  <= 1'b0;
        mod_value   <= 0;
        mod_value   <= 0;
      end
      end
    else
    else
      case (write_regs) // synopsys parallel_case
      case (write_regs) // synopsys parallel_case
         4'b0011 :
         4'b0011 :  // 16-bit write
           begin
           begin
             pit_slave   <= write_data[15];
             pit_slave   <= write_data[15];
             pit_pre     <= write_data[11:8];
             pit_pre     <= write_data[11:8];
             pit_flg_clr <= write_data[2];
             pit_flg_clr <= write_data[2];
             pit_ien     <= write_data[1];
             pit_ien     <= write_data[1];
             cnt_sync_o  <= write_data[0];
             cnt_sync_o  <= write_data[0];
           end
           end
         4'b0001 :
         4'b0001 :  // 8-bit low byte write
           begin
           begin
             pit_flg_clr <= write_data[2];
             pit_flg_clr <= write_data[2];
             pit_ien     <= write_data[1];
             pit_ien     <= write_data[1];
             cnt_sync_o  <= write_data[0];
             cnt_sync_o  <= write_data[0];
           end
           end
         4'b0010 :
         4'b0010 :  // 8-bit high byte write
           begin
           begin
             pit_slave   <= write_data[7];
             pit_slave   <= write_data[7];
             pit_pre     <= write_data[3:0];
             pit_pre     <= write_data[3:0];
           end
           end
         4'b1100 : mod_value        <= write_data;
         4'b1100 : mod_value        <= write_data;

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