URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] [trunk/] [rtl/] [sys_verilog/] [pit_regs.sv] - Diff between revs 21 and 22

Rev 21	Rev 22
Line 73...	Line 73...
`assign write_data = (DWIDTH == 8) ? {write_bus[7:0], write_bus[7:0]} : write_bus;`	`assign write_data = (DWIDTH == 8) ? {write_bus[7:0], write_bus[7:0]} : write_bus;`

`assign pit_pre_scl = NO_PRESCALE ? 4'b0 : pit_pre;`	`assign pit_pre_scl = NO_PRESCALE ? 4'b0 : pit_pre;`

`// generate wishbone write registers`	`// generate wishbone write registers`
`always @(posedge bus_clk or negedge async_rst_b)`	`always_ff @(posedge bus_clk or negedge async_rst_b)`
`if (!async_rst_b)`	`if (!async_rst_b)`
`begin`	`begin`
`pit_slave <= 1'b0;`	`pit_slave <= 1'b0;`
`pit_pre <= 4'b0;`	`pit_pre <= 4'b0;`
`pit_flg_clr <= 1'b0;`	`pit_flg_clr <= 1'b0;`
Line 121...	Line 121...
`default:`	`default:`
`pit_flg_clr <= 1'b0;`	`pit_flg_clr <= 1'b0;`
`endcase`	`endcase`

`// generate interrupt request signals`	`// generate interrupt request signals`
`always @(posedge bus_clk or negedge async_rst_b)`	`always_ff @(posedge bus_clk or negedge async_rst_b)`
`if (!async_rst_b)`	`if (!async_rst_b)`
`pit_irq_o <= 0;`	`pit_irq_o <= 0;`
`else if (sync_reset)`	`else if (sync_reset)`
`pit_irq_o <= 0;`	`pit_irq_o <= 0;`
`else`	`else`