| Line 72... |
Line 72... |
logic prescale_out; //
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logic prescale_out; //
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logic pit_flg_clr; // Clear PIT Rollover Status Bit
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logic pit_flg_clr; // Clear PIT Rollover Status Bit
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logic pit_slave; // PIT in Slave Mode, ext_sync_i selected
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logic pit_slave; // PIT in Slave Mode, ext_sync_i selected
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logic [ 3:0] pit_pre_scl; // Prescaler modulo
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logic [ 3:0] pit_pre_scl; // Prescaler modulo
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logic counter_sync; //
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logic counter_sync; //
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logic pit_flag; //
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// Wishbone Bus interface
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// Wishbone Bus interface
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pit_wb_bus #(.ARST_LVL(ARST_LVL),
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pit_wb_bus #(.ARST_LVL(ARST_LVL),
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.SINGLE_CYCLE(SINGLE_CYCLE),
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.SINGLE_CYCLE(SINGLE_CYCLE),
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.DWIDTH(DWIDTH))
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.DWIDTH(DWIDTH))
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wishbone(*,
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wishbone(
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.irq_source ( cnt_flag_o ),
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.irq_source ( cnt_flag_o ),
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.read_regs ( // in -- status register bits
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.read_regs ( // in -- status register bits
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{ cnt_n,
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{ cnt_n,
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mod_value,
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mod_value,
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{pit_slave, DECADE_CNTR, NO_PRESCALE, 1'b0, pit_pre_scl,
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{pit_slave, DECADE_CNTR, NO_PRESCALE, 1'b0, pit_pre_scl,
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5'b0, cnt_flag_o, pit_ien, cnt_sync_o}
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5'b0, cnt_flag_o, pit_ien, cnt_sync_o}
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}
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}
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)
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),
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);
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.*);
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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pit_regs #(.ARST_LVL(ARST_LVL),
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pit_regs #(.ARST_LVL(ARST_LVL),
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.COUNT_SIZE(COUNT_SIZE),
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.COUNT_SIZE(COUNT_SIZE),
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.NO_PRESCALE(NO_PRESCALE),
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.NO_PRESCALE(NO_PRESCALE),
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.DWIDTH(DWIDTH))
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.DWIDTH(DWIDTH))
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regs(*,
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regs(
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.bus_clk ( wb_clk_i ),
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.bus_clk ( wb_clk_i ),
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.write_bus ( wb_dat_i )
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.write_bus ( wb_dat_i ),
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);
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.*);
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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pit_prescale #(.COUNT_SIZE(PRE_COUNT_SIZE),
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pit_prescale #(.COUNT_SIZE(PRE_COUNT_SIZE),
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.DECADE_CNTR(DECADE_CNTR),
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.DECADE_CNTR(DECADE_CNTR),
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.NO_PRESCALE(NO_PRESCALE))
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.NO_PRESCALE(NO_PRESCALE))
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prescale(*,
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prescale(
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.bus_clk ( wb_clk_i ),
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.bus_clk ( wb_clk_i ),
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.divisor ( pit_pre_scl )
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.divisor ( pit_pre_scl ),
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);
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.*);
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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pit_count #(.COUNT_SIZE(COUNT_SIZE))
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pit_count #(.COUNT_SIZE(COUNT_SIZE))
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counter(*,
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counter(
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.bus_clk ( wb_clk_i )
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.bus_clk ( wb_clk_i ),
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);
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.*);
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|
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endmodule // pit_top
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endmodule // pit_top
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