| Line 89... |
Line 89... |
assign wb_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
|
assign wb_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
|
assign address = SINGLE_CYCLE ? wb_adr_i : addr_latch;
|
assign address = SINGLE_CYCLE ? wb_adr_i : addr_latch;
|
|
|
// generate acknowledge output signal, By using register all accesses takes two cycles.
|
// generate acknowledge output signal, By using register all accesses takes two cycles.
|
// Accesses in back to back clock cycles are not possable.
|
// Accesses in back to back clock cycles are not possable.
|
always @(posedge wb_clk_i or negedge async_rst_b)
|
always_ff @(posedge wb_clk_i or negedge async_rst_b)
|
if (!async_rst_b)
|
if (!async_rst_b)
|
bus_wait_state <= 1'b0;
|
bus_wait_state <= 1'b0;
|
else if (sync_reset)
|
else if (sync_reset)
|
bus_wait_state <= 1'b0;
|
bus_wait_state <= 1'b0;
|
else
|
else
|
bus_wait_state <= module_sel && !bus_wait_state;
|
bus_wait_state <= module_sel && !bus_wait_state;
|
|
|
// Capture address in first cycle of WISHBONE Bus tranaction
|
// Capture address in first cycle of WISHBONE Bus tranaction
|
// Only used when Wait states are enabled
|
// Only used when Wait states are enabled
|
always @(posedge wb_clk_i)
|
always_ff @(posedge wb_clk_i)
|
if ( module_sel ) // Clock gate for power saving
|
if ( module_sel ) // Clock gate for power saving
|
addr_latch <= wb_adr_i;
|
addr_latch <= wb_adr_i;
|
|
|
// WISHBONE Read Data Mux
|
// WISHBONE Read Data Mux
|
always @*
|
always_comb
|
case ({eight_bit_bus, address}) // synopsys parallel_case
|
case ({eight_bit_bus, address}) // synopsys parallel_case
|
// 8 bit Bus, 8 bit Granularity
|
// 8 bit Bus, 8 bit Granularity
|
4'b1_000: wb_dat_o = read_regs[ 7: 0]; // 8 bit read address 0
|
4'b1_000: wb_dat_o = read_regs[ 7: 0]; // 8 bit read address 0
|
4'b1_001: wb_dat_o = read_regs[15: 8]; // 8 bit read address 1
|
4'b1_001: wb_dat_o = read_regs[15: 8]; // 8 bit read address 1
|
4'b1_010: wb_dat_o = read_regs[23:16]; // 8 bit read address 2
|
4'b1_010: wb_dat_o = read_regs[23:16]; // 8 bit read address 2
|
| Line 121... |
Line 121... |
4'b0_010: wb_dat_o = read_regs[47:32];
|
4'b0_010: wb_dat_o = read_regs[47:32];
|
default: wb_dat_o = 0;
|
default: wb_dat_o = 0;
|
endcase
|
endcase
|
|
|
// generate wishbone write register strobes -- one hot if 8 bit bus
|
// generate wishbone write register strobes -- one hot if 8 bit bus
|
always @*
|
always_comb
|
begin
|
begin
|
write_regs = 0;
|
write_regs = 0;
|
if (wb_wacc)
|
if (wb_wacc)
|
case ({eight_bit_bus, address}) // synopsys parallel_case
|
case ({eight_bit_bus, address}) // synopsys parallel_case
|
// 8 bit Bus, 8 bit Granularity
|
// 8 bit Bus, 8 bit Granularity
|
