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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module pit_wb_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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interface wishbone_if #(parameter D_WIDTH = 16,
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parameter DWIDTH = 16,
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parameter A_WIDTH = 3)
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parameter SINGLE_CYCLE = 1'b0)
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// These signals maintain their direction without regard to master or slave
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// Some signals may not be connected in every instance of the interface usage
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(logic [D_WIDTH-1:0] wb_dat_i, // databus input
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logic wb_clk, // master clock input
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// These signals will change direction based on interface usage
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logic arst, // asynchronous reset
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logic wb_rst, // synchronous active high reset
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logic [A_WIDTH-1:0] wb_adr, // lower address bits
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logic wb_we, // write enable input
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logic wb_cyc, // valid bus cycle input
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logic [2:0] wb_sel // Select bytes in word bus transaction
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);
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// Define the signal directions when the interface is used as a slave
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modport slave (input wb_clk,
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arst,
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wb_rst,
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wb_adr,
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wb_dat_i,
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wb_we,
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wb_cyc,
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wb_sel);
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// define the signal directions when the interface is used as a master
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modport master (output wb_adr,
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wb_we,
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wb_cyc,
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wb_sel,
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input wb_clk,
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wb_dat_i,
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arst,
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wb_rst);
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endinterface // wishbone_if
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module pit_wb_bus #(parameter D_WIDTH = 16,
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parameter S_WIDTH = 2,
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parameter A_WIDTH = 3,
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parameter ARST_LVL = 1'b0, // asynchronous reset level
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parameter SINGLE_CYCLE = 1'b0) // Add a wait state to bus transcation
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(
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(
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// Wishbone Signals
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// Wishbone Signals
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output logic [DWIDTH-1:0] wb_dat_o, // databus output - Pseudo Register
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wishbone_if.slave wb, // Define the interface instance name
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output wb_ack_o, // bus cycle acknowledge output
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output logic [D_WIDTH-1:0] wb_dat_o, // databus output - Pseudo Register
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input wb_clk_i, // master clock input
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output logic wb_ack, // bus cycle acknowledge output
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input wb_rst_i, // synchronous active high reset
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input logic wb_stb, // stobe/core select signal
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input arst_i, // asynchronous reset
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input [ 2:0] wb_adr_i, // lower address bits
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input [DWIDTH-1:0] wb_dat_i, // databus input
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input wb_we_i, // write enable input
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input wb_stb_i, // stobe/core select signal
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input wb_cyc_i, // valid bus cycle input
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input [1:0] wb_sel_i, // Select byte in word bus transaction
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// PIT Control Signals
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// PIT Control Signals
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output logic [ 3:0] write_regs, // Decode write control register
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output logic [ 3:0] write_regs, // Decode write control register
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output async_rst_b, //
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output async_rst_b, //
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output sync_reset, //
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output sync_reset, //
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input irq_source, //
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input irq_source, //
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input [47:0] read_regs // status register bits
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input [47:0] read_regs // status register bits
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);
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);
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// registers
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// registers
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logic bus_wait_state; // Holdoff wb_ack_o for one clock to add wait state
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logic bus_wait_state; // Holdoff wb_ack for one clock to add wait state
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logic [2:0] addr_latch; // Capture WISHBONE Address
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logic [2:0] addr_latch; // Capture WISHBONE Address
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// Wires
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// Wires
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logic eight_bit_bus;
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logic eight_bit_bus;
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logic module_sel; // This module is selected for bus transaction
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logic module_sel; // This module is selected for bus transaction
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//
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//
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// module body
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// module body
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//
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//
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// generate internal resets
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// generate internal resets
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assign eight_bit_bus = (DWIDTH == 8);
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assign eight_bit_bus = (D_WIDTH == 8);
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assign async_rst_b = arst_i ^ ARST_LVL;
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assign async_rst_b = wb.arst ^ ARST_LVL;
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assign sync_reset = wb_rst_i;
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assign sync_reset = wb.wb_rst;
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// generate wishbone signals
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// generate wishbone signals
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assign module_sel = wb_cyc_i && wb_stb_i;
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assign module_sel = wb.wb_cyc && wb_stb;
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assign wb_wacc = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
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assign wb_wacc = module_sel && wb.wb_we && (wb_ack || SINGLE_CYCLE);
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assign wb_racc = module_sel && !wb_we_i;
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assign wb_racc = module_sel && !wb.wb_we;
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assign wb_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
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assign wb_ack = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
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assign address = SINGLE_CYCLE ? wb_adr_i : addr_latch;
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assign address = SINGLE_CYCLE ? wb.wb_adr : addr_latch;
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// generate acknowledge output signal, By using register all accesses takes two cycles.
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// generate acknowledge output signal, By using register all accesses takes two cycles.
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// Accesses in back to back clock cycles are not possable.
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// Accesses in back to back clock cycles are not possable.
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always_ff @(posedge wb_clk_i or negedge async_rst_b)
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always_ff @(posedge wb.wb_clk or negedge async_rst_b)
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if (!async_rst_b)
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if (!async_rst_b)
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bus_wait_state <= 1'b0;
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bus_wait_state <= 1'b0;
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else if (sync_reset)
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else if (sync_reset)
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bus_wait_state <= 1'b0;
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bus_wait_state <= 1'b0;
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else
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else
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bus_wait_state <= module_sel && !bus_wait_state;
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bus_wait_state <= module_sel && !bus_wait_state;
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// Capture address in first cycle of WISHBONE Bus tranaction
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// Capture address in first cycle of WISHBONE Bus tranaction
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// Only used when Wait states are enabled
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// Only used when Wait states are enabled
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always_ff @(posedge wb_clk_i)
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// Synthesis tool should be enabled to remove these registers in SINGLE_CYCLE mode
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always_ff @(posedge wb.wb_clk)
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if ( module_sel ) // Clock gate for power saving
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if ( module_sel ) // Clock gate for power saving
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addr_latch <= wb_adr_i;
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addr_latch <= wb.wb_adr;
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// WISHBONE Read Data Mux
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// WISHBONE Read Data Mux
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always_comb
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always_comb
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case ({eight_bit_bus, address}) // synopsys parallel_case
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case ({eight_bit_bus, address}) // synopsys parallel_case
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// 8 bit Bus, 8 bit Granularity
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// 8 bit Bus, 8 bit Granularity
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4'b1_101: wb_dat_o = read_regs[47:40]; // 8 bit read address 5
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4'b1_101: wb_dat_o = read_regs[47:40]; // 8 bit read address 5
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// 16 bit Bus, 16 bit Granularity
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// 16 bit Bus, 16 bit Granularity
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4'b0_000: wb_dat_o = read_regs[15: 0]; // 16 bit read access address 0
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4'b0_000: wb_dat_o = read_regs[15: 0]; // 16 bit read access address 0
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4'b0_001: wb_dat_o = read_regs[31:16];
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4'b0_001: wb_dat_o = read_regs[31:16];
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4'b0_010: wb_dat_o = read_regs[47:32];
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4'b0_010: wb_dat_o = read_regs[47:32];
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default: wb_dat_o = 0;
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default: wb_dat_o = '0;
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endcase
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endcase
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// generate wishbone write register strobes -- one hot if 8 bit bus
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// generate wishbone write register strobes -- one hot if 8 bit bus
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always_comb
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always_comb
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begin
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begin
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