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[/] [pit/] [trunk/] [rtl/] [verilog/] [pit_top.v] - Diff between revs 2 and 10

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Rev 2 Rev 10
Line 39... Line 39...
module pit_top #(parameter ARST_LVL = 1'b0,      // asynchronous reset level
module pit_top #(parameter ARST_LVL = 1'b0,      // asynchronous reset level
                 parameter PRE_COUNT_SIZE = 15,  // Prescale Counter size
                 parameter PRE_COUNT_SIZE = 15,  // Prescale Counter size
                 parameter COUNT_SIZE = 16,      // Main counter size
                 parameter COUNT_SIZE = 16,      // Main counter size
                 parameter DECADE_CNTR = 1'b1,   // Prescale rollover decode
                 parameter DECADE_CNTR = 1'b1,   // Prescale rollover decode
                 parameter NO_PRESCALE = 1'b0,   // Remove prescale function
                 parameter NO_PRESCALE = 1'b0,   // Remove prescale function
 
                 parameter SINGLE_CYCLE = 1'b0,  // No bus wait state added
                 parameter DWIDTH = 16)          // Data bus width
                 parameter DWIDTH = 16)          // Data bus width
  (
  (
  // Wishbone Signals
  // Wishbone Signals
  output [DWIDTH-1:0] wb_dat_o,     // databus output
  output [DWIDTH-1:0] wb_dat_o,     // databus output
  output              wb_ack_o,     // bus cycle acknowledge output
  output              wb_ack_o,     // bus cycle acknowledge output
Line 74... Line 75...
  wire           [ 3:0] pit_pre_scl;   // Prescaler modulo
  wire           [ 3:0] pit_pre_scl;   // Prescaler modulo
  wire                  counter_sync;  // 
  wire                  counter_sync;  // 
 
 
  // Wishbone Bus interface
  // Wishbone Bus interface
  pit_wb_bus #(.ARST_LVL(ARST_LVL),
  pit_wb_bus #(.ARST_LVL(ARST_LVL),
 
               .SINGLE_CYCLE(SINGLE_CYCLE),
               .DWIDTH(DWIDTH))
               .DWIDTH(DWIDTH))
    wishbone(
    wishbone(
    .wb_dat_o     ( wb_dat_o ),
    .wb_dat_o     ( wb_dat_o ),
    .wb_ack_o     ( wb_ack_o ),
    .wb_ack_o     ( wb_ack_o ),
    .wb_clk_i     ( wb_clk_i ),
    .wb_clk_i     ( wb_clk_i ),

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