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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module pit_wb_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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module pit_wb_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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parameter DWIDTH = 16)
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parameter DWIDTH = 16,
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parameter SINGLE_CYCLE = 1'b0)
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(
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(
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// Wishbone Signals
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// Wishbone Signals
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output reg [DWIDTH-1:0] wb_dat_o, // databus output
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output reg [DWIDTH-1:0] wb_dat_o, // databus output
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output reg wb_ack_o, // bus cycle acknowledge output
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output wb_ack_o, // bus cycle acknowledge output
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input wb_clk_i, // master clock input
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input wb_clk_i, // master clock input
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input wb_rst_i, // synchronous active high reset
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input wb_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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input arst_i, // asynchronous reset
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input [ 2:0] wb_adr_i, // lower address bits
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input [ 2:0] wb_adr_i, // lower address bits
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input [DWIDTH-1:0] wb_dat_i, // databus input
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input [DWIDTH-1:0] wb_dat_i, // databus input
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input [47:0] read_regs // status register bits
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input [47:0] read_regs // status register bits
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);
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);
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// registers
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// registers
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reg bus_wait_state; // Holdoff wb_ack_o for one clock to add wait state
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// Wires
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// Wires
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wire eight_bit_bus;
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wire eight_bit_bus;
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wire wb_wacc; // WISHBONE Write Strobe
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//
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//
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// module body
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// module body
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//
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//
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assign async_rst_b = arst_i ^ ARST_LVL;
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assign async_rst_b = arst_i ^ ARST_LVL;
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assign sync_reset = wb_rst_i;
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assign sync_reset = wb_rst_i;
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// generate wishbone signals
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// generate wishbone signals
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wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i & wb_ack_o;
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assign wb_wacc = wb_cyc_i && wb_stb_i && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
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assign wb_ack_o = SINGLE_CYCLE ? wb_cyc_i && wb_stb_i : bus_wait_state;
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// generate acknowledge output signal
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// generate acknowledge output signal, By using register all accesses takes two cycles.
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always @(posedge wb_clk_i)
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// Accesses in back to back clock cycles are not possable.
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wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
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always @(posedge wb_clk_i or negedge async_rst_b)
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if (!async_rst_b)
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bus_wait_state <= 1'b0;
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else if (sync_reset)
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bus_wait_state <= 1'b0;
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else
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bus_wait_state <= wb_cyc_i && wb_stb_i && !bus_wait_state;
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// assign data read bus -- DAT_O
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// assign data read bus -- DAT_O
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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case ({eight_bit_bus, wb_adr_i}) // synopsys parallel_case
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case ({eight_bit_bus, wb_adr_i}) // synopsys parallel_case
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// 8 bit Bus, 8 bit Granularity
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// 8 bit Bus, 8 bit Granularity
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