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[/] [pit/] [trunk/] [rtl/] [verilog/] [pit_wb_bus.v] - Diff between revs 14 and 17
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Rev 14 |
Rev 17 |
Line 84... |
Line 84... |
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// generate wishbone signals
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// generate wishbone signals
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assign module_sel = wb_cyc_i && wb_stb_i;
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assign module_sel = wb_cyc_i && wb_stb_i;
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assign wb_wacc = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
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assign wb_wacc = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
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assign wb_racc = module_sel && !wb_we_i;
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assign wb_racc = module_sel && !wb_we_i;
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assign wb_ack_o = SINGLE_CYCLE ? module_sel : bus_wait_state;
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assign wb_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
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assign wb_dat_o = SINGLE_CYCLE ? rd_data_mux : rd_data_reg;
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assign wb_dat_o = SINGLE_CYCLE ? rd_data_mux : rd_data_reg;
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// generate acknowledge output signal, By using register all accesses takes two cycles.
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// generate acknowledge output signal, By using register all accesses takes two cycles.
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// Accesses in back to back clock cycles are not possable.
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// Accesses in back to back clock cycles are not possable.
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always @(posedge wb_clk_i or negedge async_rst_b)
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always @(posedge wb_clk_i or negedge async_rst_b)
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