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[/] [pit/] [trunk/] [rtl/] [verilog/] [pit_wb_bus.v] - Diff between revs 17 and 18

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Rev 17 Rev 18
Line 39... Line 39...
module pit_wb_bus #(parameter ARST_LVL = 1'b0,    // asynchronous reset level
module pit_wb_bus #(parameter ARST_LVL = 1'b0,    // asynchronous reset level
                    parameter DWIDTH = 16,
                    parameter DWIDTH = 16,
                    parameter SINGLE_CYCLE = 1'b0)
                    parameter SINGLE_CYCLE = 1'b0)
  (
  (
  // Wishbone Signals
  // Wishbone Signals
  output      [DWIDTH-1:0] wb_dat_o,     // databus output
  output reg  [DWIDTH-1:0] wb_dat_o,     // databus output - Pseudo Register
  output                   wb_ack_o,     // bus cycle acknowledge output
  output                   wb_ack_o,     // bus cycle acknowledge output
  input                    wb_clk_i,     // master clock input
  input                    wb_clk_i,     // master clock input
  input                    wb_rst_i,     // synchronous active high reset
  input                    wb_rst_i,     // synchronous active high reset
  input                    arst_i,       // asynchronous reset
  input                    arst_i,       // asynchronous reset
  input             [ 2:0] wb_adr_i,     // lower address bits
  input             [ 2:0] wb_adr_i,     // lower address bits
Line 61... Line 61...
  );
  );
 
 
 
 
  // registers
  // registers
  reg                bus_wait_state;  // Holdoff wb_ack_o for one clock to add wait state
  reg                bus_wait_state;  // Holdoff wb_ack_o for one clock to add wait state
  reg  [DWIDTH-1:0]  rd_data_mux;     // Pseudo Register, WISHBONE Read Data Mux
  reg  [2:0] addr_latch;      // Capture WISHBONE Address 
  reg  [DWIDTH-1:0]  rd_data_reg;     // Latch for WISHBONE Read Data
 
 
 
  // Wires
  // Wires
  wire   eight_bit_bus;
  wire   eight_bit_bus;
  wire   module_sel;      // This module is selected for bus transaction
  wire   module_sel;      // This module is selected for bus transaction
  wire   wb_wacc;         // WISHBONE Write Strobe
  wire   wb_wacc;         // WISHBONE Write Strobe
  wire   wb_racc;         // WISHBONE Read Access (Clock gating signal)
  wire   wb_racc;         // WISHBONE Read Access (Clock gating signal)
 
  wire [2:0] address;         // Select either direct or latched address
 
 
  //
  //
  // module body
  // module body
  //
  //
 
 
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  // generate wishbone signals
  // generate wishbone signals
  assign module_sel = wb_cyc_i && wb_stb_i;
  assign module_sel = wb_cyc_i && wb_stb_i;
  assign wb_wacc    = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
  assign wb_wacc    = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
  assign wb_racc    = module_sel && !wb_we_i;
  assign wb_racc    = module_sel && !wb_we_i;
  assign wb_ack_o   = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
  assign wb_ack_o   = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
  assign wb_dat_o   = SINGLE_CYCLE ? rd_data_mux : rd_data_reg;
  assign address    = SINGLE_CYCLE ? wb_adr_i : addr_latch;
 
 
  // generate acknowledge output signal, By using register all accesses takes two cycles.
  // generate acknowledge output signal, By using register all accesses takes two cycles.
  //  Accesses in back to back clock cycles are not possable.
  //  Accesses in back to back clock cycles are not possable.
  always @(posedge wb_clk_i or negedge async_rst_b)
  always @(posedge wb_clk_i or negedge async_rst_b)
    if (!async_rst_b)
    if (!async_rst_b)
Line 97... Line 97...
    else if (sync_reset)
    else if (sync_reset)
      bus_wait_state <=  1'b0;
      bus_wait_state <=  1'b0;
    else
    else
      bus_wait_state <=  module_sel && !bus_wait_state;
      bus_wait_state <=  module_sel && !bus_wait_state;
 
 
  // assign data read bus -- DAT_O
  // Capture address in first cycle of WISHBONE Bus tranaction
 
  //  Only used when Wait states are enabled
  always @(posedge wb_clk_i)
  always @(posedge wb_clk_i)
    if ( wb_racc )                     // Clock gate for power saving
    if ( module_sel )                  // Clock gate for power saving
      rd_data_reg <= rd_data_mux;
      addr_latch <= wb_adr_i;
 
 
  // WISHBONE Read Data Mux
  // WISHBONE Read Data Mux
  always @*
  always @*
      case ({eight_bit_bus, wb_adr_i}) // synopsys parallel_case
      case ({eight_bit_bus, address}) // synopsys parallel_case
      // 8 bit Bus, 8 bit Granularity
      // 8 bit Bus, 8 bit Granularity
      4'b1_000: rd_data_mux = read_regs[ 7: 0];  // 8 bit read address 0
      4'b1_000: wb_dat_o = read_regs[ 7: 0];  // 8 bit read address 0
      4'b1_001: rd_data_mux = read_regs[15: 8];  // 8 bit read address 1
      4'b1_001: wb_dat_o = read_regs[15: 8];  // 8 bit read address 1
      4'b1_010: rd_data_mux = read_regs[23:16];  // 8 bit read address 2
      4'b1_010: wb_dat_o = read_regs[23:16];  // 8 bit read address 2
      4'b1_011: rd_data_mux = read_regs[31:24];  // 8 bit read address 3
      4'b1_011: wb_dat_o = read_regs[31:24];  // 8 bit read address 3
      4'b1_100: rd_data_mux = read_regs[39:32];  // 8 bit read address 4
      4'b1_100: wb_dat_o = read_regs[39:32];  // 8 bit read address 4
      4'b1_101: rd_data_mux = read_regs[47:40];  // 8 bit read address 5
      4'b1_101: wb_dat_o = read_regs[47:40];  // 8 bit read address 5
      // 16 bit Bus, 16 bit Granularity
      // 16 bit Bus, 16 bit Granularity
      4'b0_000: rd_data_mux = read_regs[15: 0];  // 16 bit read access address 0
      4'b0_000: wb_dat_o = read_regs[15: 0];  // 16 bit read access address 0
      4'b0_001: rd_data_mux = read_regs[31:16];
      4'b0_001: wb_dat_o = read_regs[31:16];
      4'b0_010: rd_data_mux = read_regs[47:32];
      4'b0_010: wb_dat_o = read_regs[47:32];
    endcase
    endcase
 
 
  // generate wishbone write register strobes -- one hot if 8 bit bus
  // generate wishbone write register strobes -- one hot if 8 bit bus
  always @*
  always @*
    begin
    begin
      write_regs = 0;
      write_regs = 0;
      if (wb_wacc)
      if (wb_wacc)
        case ({eight_bit_bus, wb_adr_i}) // synopsys parallel_case
        case ({eight_bit_bus, address}) // synopsys parallel_case
           // 8 bit Bus, 8 bit Granularity
           // 8 bit Bus, 8 bit Granularity
           4'b1_000 : write_regs = 4'b0001;
           4'b1_000 : write_regs = 4'b0001;
           4'b1_001 : write_regs = 4'b0010;
           4'b1_001 : write_regs = 4'b0010;
           4'b1_010 : write_regs = 4'b0100;
           4'b1_010 : write_regs = 4'b0100;
           4'b1_011 : write_regs = 4'b1000;
           4'b1_011 : write_regs = 4'b1000;

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