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module pit_wb_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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module pit_wb_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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parameter DWIDTH = 16,
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parameter DWIDTH = 16,
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parameter SINGLE_CYCLE = 1'b0)
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parameter SINGLE_CYCLE = 1'b0)
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(
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(
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// Wishbone Signals
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// Wishbone Signals
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output [DWIDTH-1:0] wb_dat_o, // databus output
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output reg [DWIDTH-1:0] wb_dat_o, // databus output - Pseudo Register
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output wb_ack_o, // bus cycle acknowledge output
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output wb_ack_o, // bus cycle acknowledge output
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input wb_clk_i, // master clock input
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input wb_clk_i, // master clock input
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input wb_rst_i, // synchronous active high reset
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input wb_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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input arst_i, // asynchronous reset
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input [ 2:0] wb_adr_i, // lower address bits
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input [ 2:0] wb_adr_i, // lower address bits
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);
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);
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// registers
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// registers
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reg bus_wait_state; // Holdoff wb_ack_o for one clock to add wait state
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reg bus_wait_state; // Holdoff wb_ack_o for one clock to add wait state
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reg [DWIDTH-1:0] rd_data_mux; // Pseudo Register, WISHBONE Read Data Mux
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reg [2:0] addr_latch; // Capture WISHBONE Address
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reg [DWIDTH-1:0] rd_data_reg; // Latch for WISHBONE Read Data
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// Wires
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// Wires
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wire eight_bit_bus;
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wire eight_bit_bus;
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wire module_sel; // This module is selected for bus transaction
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wire module_sel; // This module is selected for bus transaction
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wire wb_wacc; // WISHBONE Write Strobe
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wire wb_wacc; // WISHBONE Write Strobe
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wire wb_racc; // WISHBONE Read Access (Clock gating signal)
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wire wb_racc; // WISHBONE Read Access (Clock gating signal)
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wire [2:0] address; // Select either direct or latched address
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//
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//
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// module body
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// module body
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//
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//
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// generate wishbone signals
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// generate wishbone signals
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assign module_sel = wb_cyc_i && wb_stb_i;
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assign module_sel = wb_cyc_i && wb_stb_i;
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assign wb_wacc = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
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assign wb_wacc = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
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assign wb_racc = module_sel && !wb_we_i;
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assign wb_racc = module_sel && !wb_we_i;
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assign wb_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
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assign wb_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
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assign wb_dat_o = SINGLE_CYCLE ? rd_data_mux : rd_data_reg;
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assign address = SINGLE_CYCLE ? wb_adr_i : addr_latch;
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// generate acknowledge output signal, By using register all accesses takes two cycles.
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// generate acknowledge output signal, By using register all accesses takes two cycles.
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// Accesses in back to back clock cycles are not possable.
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// Accesses in back to back clock cycles are not possable.
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always @(posedge wb_clk_i or negedge async_rst_b)
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always @(posedge wb_clk_i or negedge async_rst_b)
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if (!async_rst_b)
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if (!async_rst_b)
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else if (sync_reset)
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else if (sync_reset)
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bus_wait_state <= 1'b0;
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bus_wait_state <= 1'b0;
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else
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else
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bus_wait_state <= module_sel && !bus_wait_state;
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bus_wait_state <= module_sel && !bus_wait_state;
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// assign data read bus -- DAT_O
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// Capture address in first cycle of WISHBONE Bus tranaction
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// Only used when Wait states are enabled
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if ( wb_racc ) // Clock gate for power saving
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if ( module_sel ) // Clock gate for power saving
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rd_data_reg <= rd_data_mux;
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addr_latch <= wb_adr_i;
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// WISHBONE Read Data Mux
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// WISHBONE Read Data Mux
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always @*
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always @*
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case ({eight_bit_bus, wb_adr_i}) // synopsys parallel_case
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case ({eight_bit_bus, address}) // synopsys parallel_case
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// 8 bit Bus, 8 bit Granularity
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// 8 bit Bus, 8 bit Granularity
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4'b1_000: rd_data_mux = read_regs[ 7: 0]; // 8 bit read address 0
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4'b1_000: wb_dat_o = read_regs[ 7: 0]; // 8 bit read address 0
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4'b1_001: rd_data_mux = read_regs[15: 8]; // 8 bit read address 1
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4'b1_001: wb_dat_o = read_regs[15: 8]; // 8 bit read address 1
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4'b1_010: rd_data_mux = read_regs[23:16]; // 8 bit read address 2
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4'b1_010: wb_dat_o = read_regs[23:16]; // 8 bit read address 2
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4'b1_011: rd_data_mux = read_regs[31:24]; // 8 bit read address 3
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4'b1_011: wb_dat_o = read_regs[31:24]; // 8 bit read address 3
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4'b1_100: rd_data_mux = read_regs[39:32]; // 8 bit read address 4
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4'b1_100: wb_dat_o = read_regs[39:32]; // 8 bit read address 4
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4'b1_101: rd_data_mux = read_regs[47:40]; // 8 bit read address 5
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4'b1_101: wb_dat_o = read_regs[47:40]; // 8 bit read address 5
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// 16 bit Bus, 16 bit Granularity
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// 16 bit Bus, 16 bit Granularity
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4'b0_000: rd_data_mux = read_regs[15: 0]; // 16 bit read access address 0
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4'b0_000: wb_dat_o = read_regs[15: 0]; // 16 bit read access address 0
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4'b0_001: rd_data_mux = read_regs[31:16];
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4'b0_001: wb_dat_o = read_regs[31:16];
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4'b0_010: rd_data_mux = read_regs[47:32];
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4'b0_010: wb_dat_o = read_regs[47:32];
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endcase
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endcase
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// generate wishbone write register strobes -- one hot if 8 bit bus
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// generate wishbone write register strobes -- one hot if 8 bit bus
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always @*
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always @*
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begin
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begin
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write_regs = 0;
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write_regs = 0;
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if (wb_wacc)
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if (wb_wacc)
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case ({eight_bit_bus, wb_adr_i}) // synopsys parallel_case
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case ({eight_bit_bus, address}) // synopsys parallel_case
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// 8 bit Bus, 8 bit Granularity
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// 8 bit Bus, 8 bit Granularity
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4'b1_000 : write_regs = 4'b0001;
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4'b1_000 : write_regs = 4'b0001;
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4'b1_001 : write_regs = 4'b0010;
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4'b1_001 : write_regs = 4'b0010;
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4'b1_010 : write_regs = 4'b0100;
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4'b1_010 : write_regs = 4'b0100;
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4'b1_011 : write_regs = 4'b1000;
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4'b1_011 : write_regs = 4'b1000;
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