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[/] [pit/] [trunk/] [rtl/] [verilog/] [pit_wb_bus.v] - Diff between revs 18 and 21
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| Rev 18 |
Rev 21 |
| Line 117... |
Line 117... |
4'b1_101: wb_dat_o = read_regs[47:40]; // 8 bit read address 5
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4'b1_101: wb_dat_o = read_regs[47:40]; // 8 bit read address 5
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// 16 bit Bus, 16 bit Granularity
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// 16 bit Bus, 16 bit Granularity
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4'b0_000: wb_dat_o = read_regs[15: 0]; // 16 bit read access address 0
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4'b0_000: wb_dat_o = read_regs[15: 0]; // 16 bit read access address 0
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4'b0_001: wb_dat_o = read_regs[31:16];
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4'b0_001: wb_dat_o = read_regs[31:16];
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4'b0_010: wb_dat_o = read_regs[47:32];
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4'b0_010: wb_dat_o = read_regs[47:32];
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default: wb_dat_o = 0;
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endcase
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endcase
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// generate wishbone write register strobes -- one hot if 8 bit bus
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// generate wishbone write register strobes -- one hot if 8 bit bus
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always @*
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always @*
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begin
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begin
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