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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Controller / Opcode Decoder
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-- TITLE: Controller / Opcode Decoder
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/8/01
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-- DATE CREATED: 2/8/01
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-- FILENAME: control.vhd
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-- FILENAME: control.vhd
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-- PROJECT: MIPS CPU core
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-- PROJECT: M-lite CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
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-- MIPS Technologies does not endorse and is not associated with
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-- this project.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Controls the CPU by decoding the opcode and generating control
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-- Controls the CPU by decoding the opcode and generating control
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-- signals to the rest of the CPU.
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-- signals to the rest of the CPU.
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-- This entity decodes the MIPS opcode into a Very-Long-Word-Instruction.
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-- This entity decodes the MIPS(tm) opcode into a
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-- Very-Long-Word-Instruction.
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-- The 32-bit opcode is converted to a
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-- The 32-bit opcode is converted to a
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-- 6+6+6+16+5+2+3+3+2+2+3+2+4 = 60 bit VLWI opcode.
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-- 6+6+6+16+5+2+3+3+2+2+3+2+4 = 60 bit VLWI opcode.
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-- Based on information found in:
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-- Based on information found in:
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-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
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-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
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-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
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-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.mips_pack.all;
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use work.mlite_pack.all;
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entity control is
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entity control is
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port(opcode : in std_logic_vector(31 downto 0);
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port(opcode : in std_logic_vector(31 downto 0);
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intr_signal : in std_logic;
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intr_signal : in std_logic;
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pause_in : in std_logic;
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pause_in : in std_logic;
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