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Line 25... |
use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity control is
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entity control is
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port(opcode : in std_logic_vector(31 downto 0);
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port(opcode : in std_logic_vector(31 downto 0);
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intr_signal : in std_logic;
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intr_signal : in std_logic;
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pause_in : in std_logic;
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rs_index : out std_logic_vector(5 downto 0);
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rs_index : out std_logic_vector(5 downto 0);
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rt_index : out std_logic_vector(5 downto 0);
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rt_index : out std_logic_vector(5 downto 0);
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rd_index : out std_logic_vector(5 downto 0);
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rd_index : out std_logic_vector(5 downto 0);
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imm_out : out std_logic_vector(15 downto 0);
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imm_out : out std_logic_vector(15 downto 0);
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alu_func : out alu_function_type;
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alu_func : out alu_function_type;
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-- from_reg_source_nez, from_reg_source_eqz);
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-- from_reg_source_nez, from_reg_source_eqz);
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-- type pc_source_type is (from_inc4, from_inc8, from_reg_source,
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-- type pc_source_type is (from_inc4, from_inc8, from_reg_source,
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-- from_opcode25_0, from_branch, from_lbranch);
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-- from_opcode25_0, from_branch, from_lbranch);
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begin
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begin
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control_proc: process(opcode, intr_signal, pause_in)
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control_proc: process(opcode, intr_signal)
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variable op, func : std_logic_vector(5 downto 0);
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variable op, func : std_logic_vector(5 downto 0);
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variable rs, rt, rd : std_logic_vector(5 downto 0);
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variable rs, rt, rd : std_logic_vector(5 downto 0);
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variable rtx : std_logic_vector(4 downto 0);
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variable rtx : std_logic_vector(4 downto 0);
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variable imm : std_logic_vector(15 downto 0);
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variable imm : std_logic_vector(15 downto 0);
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variable alu_function : alu_function_type;
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variable alu_function : alu_function_type;
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when "111110" => --SDC2
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when "111110" => --SDC2
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when "111111" => --SDC3
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when "111111" => --SDC3
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when others =>
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when others =>
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end case;
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end case;
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if c_source = c_from_null or pause_in = '1' then
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if c_source = c_from_null then
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rd := "000000";
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rd := "000000";
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end if;
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end if;
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if intr_signal = '1' then
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if intr_signal = '1' then
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rs := "111111"; --interrupt vector
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rs := "111111"; --interrupt vector
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