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VHD = mips_pack alu bus_mux control mem_ctrl mult pc_next reg_bank shifter \
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#Makefile for MIPS-lite
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mips_cpu
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all: work/tbench/_primary.dat
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#for ModelSim
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#WORK_DIR = work
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work/mips_pack/_primary.dat: mips_pack.vhd
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#DEP_FILE = _primary.dat
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vcom -check_synthesis mips_pack.vhd
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#COMPILE = vcom -check_synthesis
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work/alu/_primary.dat: mips_pack.vhd alu.vhd
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#for FREE VHDL simulator http://www.symphonyeda.com
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vcom -check_synthesis alu.vhd
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WORK_DIR = work.sym
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DEP_FILE = prim.dep
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work/bus_mux/_primary.dat: mips_pack.vhd bus_mux.vhd
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COMPILE = vhdlp -s
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vcom -check_synthesis bus_mux.vhd
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all: $(WORK_DIR)/tbench/$(DEP_FILE)
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work/control/_primary.dat: mips_pack.vhd control.vhd
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vcom -check_synthesis control.vhd
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run: all
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-@echo off > output.txt
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work/mem_ctrl/_primary.dat: mips_pack.vhd mem_ctrl.vhd
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-@echo on
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vcom -check_synthesis mem_ctrl.vhd
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-@start tail -f output.txt
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vhdle -t 10ms tbench
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work/mult/_primary.dat: mips_pack.vhd mult.vhd
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-@diff output.txt ../tools/output.txt
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vcom -check_synthesis mult.vhd
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simulate: all
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work/pc_next/_primary.dat: mips_pack.vhd pc_next.vhd
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vhdle -s -t 10us tbench -do simili.cmd -list trace.txt
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vcom -check_synthesis pc_next.vhd
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-@..\tools\tracehex
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-@ed trace2.txt
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work/reg_bank/_primary.dat: mips_pack.vhd reg_bank.vhd
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vcom -check_synthesis reg_bank.vhd
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$(WORK_DIR)/mips_pack/$(DEP_FILE): mips_pack.vhd
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$(COMPILE) mips_pack.vhd
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work/shifter/_primary.dat: mips_pack.vhd shifter.vhd
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vcom -check_synthesis shifter.vhd
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$(WORK_DIR)/alu/$(DEP_FILE): mips_pack.vhd alu.vhd
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$(COMPILE) alu.vhd
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work/mips_cpu/_primary.dat: mips_cpu.vhd \
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work/mips_pack/_primary.dat \
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$(WORK_DIR)/bus_mux/$(DEP_FILE): mips_pack.vhd bus_mux.vhd
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work/alu/_primary.dat \
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$(COMPILE) bus_mux.vhd
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work/bus_mux/_primary.dat \
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work/control/_primary.dat \
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$(WORK_DIR)/control/$(DEP_FILE): mips_pack.vhd control.vhd
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work/mem_ctrl/_primary.dat \
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$(COMPILE) control.vhd
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work/mult/_primary.dat \
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work/pc_next/_primary.dat \
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$(WORK_DIR)/mem_ctrl/$(DEP_FILE): mips_pack.vhd mem_ctrl.vhd
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work/reg_bank/_primary.dat \
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$(COMPILE) mem_ctrl.vhd
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work/shifter/_primary.dat
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vcom -check_synthesis mips_cpu.vhd
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$(WORK_DIR)/mult/$(DEP_FILE): mips_pack.vhd mult.vhd
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$(COMPILE) mult.vhd
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work/ram/_primary.dat: ram.vhd
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vcom -explicit ram.vhd
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$(WORK_DIR)/pc_next/$(DEP_FILE): mips_pack.vhd pc_next.vhd
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$(COMPILE) pc_next.vhd
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work/tbench/_primary.dat: tbench.vhd \
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work/mips_cpu/_primary.dat \
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$(WORK_DIR)/reg_bank/$(DEP_FILE): mips_pack.vhd reg_bank.vhd
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work/ram/_primary.dat
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$(COMPILE) reg_bank.vhd
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vcom tbench.vhd
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$(WORK_DIR)/shifter/$(DEP_FILE): mips_pack.vhd shifter.vhd
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$(COMPILE) shifter.vhd
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$(WORK_DIR)/mips_cpu/$(DEP_FILE): mips_cpu.vhd \
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$(WORK_DIR)/mips_pack/$(DEP_FILE) \
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$(WORK_DIR)/alu/$(DEP_FILE) \
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$(WORK_DIR)/bus_mux/$(DEP_FILE) \
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$(WORK_DIR)/control/$(DEP_FILE) \
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$(WORK_DIR)/mem_ctrl/$(DEP_FILE) \
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$(WORK_DIR)/mult/$(DEP_FILE) \
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$(WORK_DIR)/pc_next/$(DEP_FILE) \
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$(WORK_DIR)/reg_bank/$(DEP_FILE) \
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$(WORK_DIR)/shifter/$(DEP_FILE)
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$(COMPILE) mips_cpu.vhd
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$(WORK_DIR)/ram/$(DEP_FILE): mips_pack.vhd ram.vhd
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$(COMPILE) -87 ram.vhd
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$(WORK_DIR)/tbench/$(DEP_FILE): mips_pack.vhd tbench.vhd \
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$(WORK_DIR)/mips_pack/$(DEP_FILE) \
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$(WORK_DIR)/mips_cpu/$(DEP_FILE) \
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$(WORK_DIR)/ram/$(DEP_FILE)
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$(COMPILE) tbench.vhd
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