| Line 45... |
Line 45... |
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
|
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
|
signal write_enable : std_logic;
|
signal write_enable : std_logic;
|
-- signal sig_false : std_logic := '0';
|
-- signal sig_false : std_logic := '0';
|
-- signal sig_true : std_logic := '1';
|
-- signal sig_true : std_logic := '1';
|
-- signal zero_sig : std_logic_vector(15 downto 0) := ZERO(15 downto 0);
|
-- signal zero_sig : std_logic_vector(15 downto 0) := ZERO(15 downto 0);
|
|
|
begin
|
begin
|
|
|
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
|
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
|
intr_enable_reg, data_out1, data_out2, reset_in, pause)
|
intr_enable_reg, data_out1, data_out2, reset_in, pause)
|
begin
|
begin
|
| Line 97... |
Line 98... |
|
|
intr_enable <= intr_enable_reg;
|
intr_enable <= intr_enable_reg;
|
end process;
|
end process;
|
|
|
|
|
------------------------------------------------------------
|
--------------------------------------------------------------
|
-- Pick only ONE of the dual-port RAM implementations below!
|
---- Pick only ONE of the dual-port RAM implementations below!
|
------------------------------------------------------------
|
--------------------------------------------------------------
|
|
|
|
-- synopsys synthesis_off
|
|
|
-- Option #1
|
-- Option #1
|
-- One tri-port RAM, two read-ports, one write-port
|
-- One tri-port RAM, two read-ports, one write-port
|
-- 32 registers 32-bits wide
|
-- 32 registers 32-bits wide
|
tri_port_mem:
|
tri_port_mem:
|
| Line 145... |
Line 147... |
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
end generate; --dual_port_mem
|
end generate; --dual_port_mem
|
|
|
|
-- synopsys synthesis_on
|
|
|
|
dual_port_mem_coregen:
|
|
if memory_type = "DUAL_PORT_XILINX" generate
|
|
|
|
reg_file_dp_ram_1: reg_file_dp_ram
|
|
port map (
|
|
addra => addr_a1,
|
|
addrb => addr_b,
|
|
clka => clk,
|
|
clkb => clk,
|
|
dinb => reg_dest_new,
|
|
douta => data_out1,
|
|
web => write_enable);
|
|
|
|
reg_file_dp_ram_2: reg_file_dp_ram
|
|
port map (
|
|
addra => addr_a2,
|
|
addrb => addr_b,
|
|
clka => clk,
|
|
clkb => clk,
|
|
dinb => reg_dest_new,
|
|
douta => data_out2,
|
|
web => write_enable);
|
|
|
|
end generate; --dual_port_mem
|
|
|
|
dual_port_mem_xc4000xla: if memory_type = "DUAL_PORT_XILINX_XC4000XLA" generate
|
|
|
|
reg_file_dp_ram_1: reg_file_dp_ram_xc4000xla
|
|
port map (
|
|
A => addr_b,
|
|
DI => reg_dest_new,
|
|
WR_EN => write_enable,
|
|
WR_CLK => clk,
|
|
DPRA => addr_a1,
|
|
SPO => open,
|
|
DPO => data_out1);
|
|
|
|
reg_file_dp_ram_2: reg_file_dp_ram_xc4000xla
|
|
port map (
|
|
A => addr_b,
|
|
DI => reg_dest_new,
|
|
WR_EN => write_enable,
|
|
WR_CLK => clk,
|
|
DPRA => addr_a2,
|
|
SPO => open,
|
|
DPO => data_out2);
|
|
|
|
end generate; --dual_port_mem
|
|
|
-- Option #3
|
-- Option #3
|
-- Generic Two-Port Synchronous RAM
|
-- Generic Two-Port Synchronous RAM
|
-- generic_tpram can be obtained from:
|
-- generic_tpram can be obtained from:
|
-- http://www.opencores.org/cvsweb.shtml/generic_memories/
|
-- http://www.opencores.org/cvsweb.shtml/generic_memories/
|
| Line 261... |
Line 313... |
-- enb => sig_true,
|
-- enb => sig_true,
|
-- web => write_enable);
|
-- web => write_enable);
|
-- end generate; --xilinx_mem
|
-- end generate; --xilinx_mem
|
|
|
|
|
-- Option #5
|
-- -- Option #5
|
-- Altera LPM_RAM_DP
|
-- -- Altera LPM_RAM_DP
|
altera_mem:
|
-- altera_mem:
|
if memory_type = "ALTERA" generate
|
-- if memory_type = "ALTERA" generate
|
lpm_ram_dp_component1 : lpm_ram_dp
|
-- lpm_ram_dp_component1 : lpm_ram_dp
|
GENERIC MAP (
|
-- GENERIC MAP (
|
lpm_width => 32,
|
-- lpm_width => 32,
|
lpm_widthad => 5,
|
-- lpm_widthad => 5,
|
rden_used => "FALSE",
|
-- rden_used => "FALSE",
|
intended_device_family => "UNUSED",
|
-- intended_device_family => "UNUSED",
|
lpm_indata => "REGISTERED",
|
-- lpm_indata => "REGISTERED",
|
lpm_wraddress_control => "REGISTERED",
|
-- lpm_wraddress_control => "REGISTERED",
|
lpm_rdaddress_control => "UNREGISTERED",
|
-- lpm_rdaddress_control => "UNREGISTERED",
|
lpm_outdata => "UNREGISTERED",
|
-- lpm_outdata => "UNREGISTERED",
|
use_eab => "ON",
|
-- use_eab => "ON",
|
lpm_type => "LPM_RAM_DP"
|
-- lpm_type => "LPM_RAM_DP"
|
)
|
-- )
|
PORT MAP (
|
-- PORT MAP (
|
wren => write_enable,
|
-- wren => write_enable,
|
wrclock => clk,
|
-- wrclock => clk,
|
data => reg_dest_new,
|
-- data => reg_dest_new,
|
rdaddress => addr_a1,
|
-- rdaddress => addr_a1,
|
wraddress => addr_b,
|
-- wraddress => addr_b,
|
q => data_out1
|
-- q => data_out1
|
);
|
-- );
|
lpm_ram_dp_component2 : lpm_ram_dp
|
-- lpm_ram_dp_component2 : lpm_ram_dp
|
GENERIC MAP (
|
-- GENERIC MAP (
|
lpm_width => 32,
|
-- lpm_width => 32,
|
lpm_widthad => 5,
|
-- lpm_widthad => 5,
|
rden_used => "FALSE",
|
-- rden_used => "FALSE",
|
intended_device_family => "UNUSED",
|
-- intended_device_family => "UNUSED",
|
lpm_indata => "REGISTERED",
|
-- lpm_indata => "REGISTERED",
|
lpm_wraddress_control => "REGISTERED",
|
-- lpm_wraddress_control => "REGISTERED",
|
lpm_rdaddress_control => "UNREGISTERED",
|
-- lpm_rdaddress_control => "UNREGISTERED",
|
lpm_outdata => "UNREGISTERED",
|
-- lpm_outdata => "UNREGISTERED",
|
use_eab => "ON",
|
-- use_eab => "ON",
|
lpm_type => "LPM_RAM_DP"
|
-- lpm_type => "LPM_RAM_DP"
|
)
|
-- )
|
PORT MAP (
|
-- PORT MAP (
|
wren => write_enable,
|
-- wren => write_enable,
|
wrclock => clk,
|
-- wrclock => clk,
|
data => reg_dest_new,
|
-- data => reg_dest_new,
|
rdaddress => addr_a2,
|
-- rdaddress => addr_a2,
|
wraddress => addr_b,
|
-- wraddress => addr_b,
|
q => data_out2
|
-- q => data_out2
|
);
|
-- );
|
end generate; --altera_mem
|
-- end generate; --altera_mem
|
|
|
end; --architecture ram_block
|
end; --architecture ram_block
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
