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-- TITLE: Register Bank

-- TITLE: Register Bank

-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)

-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)

-- DATE CREATED: 2/2/01

-- DATE CREATED: 2/2/01

-- FILENAME: reg_bank.vhd

-- FILENAME: reg_bank.vhd

-- COPYRIGHT: Software placed into the public domain by the author.

-- COPYRIGHT: Software placed into the public domain by the author.

--    Software 'as is' without warranty.  Author liable for nothing.

--    Software 'as is' without warranty.  Author liable for nothing.

-- DESCRIPTION:

-- DESCRIPTION:

--    Implements a register bank with 32 registers that are 32-bits wide.

--    Implements a register bank with 32 registers that are 32-bits wide.

--    There are two read-ports and one write port.

--    There are two read-ports and one write port.

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library ieee;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_unsigned.all;

entity reg_bank is

entity reg_bank is

   port(clk            : in  std_logic;

   port(clk            : in  std_logic;

        reset_in       : in  std_logic;

        reset_in       : in  std_logic;

        rs_index       : in  std_logic_vector(5 downto 0);

        rs_index       : in  std_logic_vector(5 downto 0);