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[/] [plasma/] [tags/] [V2_1/] [vhdl/] [reg_bank.vhd] - Diff between revs 24 and 39
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-- TITLE: Register Bank
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-- TITLE: Register Bank
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/2/01
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-- DATE CREATED: 2/2/01
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-- FILENAME: reg_bank.vhd
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-- FILENAME: reg_bank.vhd
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-- PROJECT: MIPS CPU core
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-- PROJECT: M-lite CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Implements a register bank with 32 registers that are 32-bits wide.
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-- Implements a register bank with 32 registers that are 32-bits wide.
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-- There are two read-ports and one write port.
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-- There are two read-ports and one write port.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mips_pack.all;
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use work.mlite_pack.all;
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entity reg_bank is
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entity reg_bank is
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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rs_index : in std_logic_vector(5 downto 0);
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rs_index : in std_logic_vector(5 downto 0);
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