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[/] [plasma/] [tags/] [V2_1/] [vhdl/] [reg_bank.vhd] - Diff between revs 74 and 88

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Rev 74 Rev 88
Line 44... Line 44...
   signal addr_a1, addr_a2, addr_b : std_logic_vector(4 downto 0);
   signal addr_a1, addr_a2, addr_b : std_logic_vector(4 downto 0);
   signal data_out1, data_out2     : std_logic_vector(31 downto 0);
   signal data_out1, data_out2     : std_logic_vector(31 downto 0);
   signal write_enable             : std_logic;
   signal write_enable             : std_logic;
--   signal sig_false                : std_logic := '0';
--   signal sig_false                : std_logic := '0';
--   signal sig_true                 : std_logic := '1';
--   signal sig_true                 : std_logic := '1';
--   signal zero_sig                 : std_logic_vector(15 downto 0) := ZERP(15 downto 0);
--   signal zero_sig                 : std_logic_vector(15 downto 0) := ZERO(15 downto 0);
begin
begin
 
 
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
      intr_enable_reg, data_out1, data_out2, reset_in)
      intr_enable_reg, data_out1, data_out2, reset_in, pause)
begin
begin
   --setup for first dual-port memory
   --setup for first dual-port memory
   if rs_index = "101110" then  --reg_epc CP0 14
   if rs_index = "101110" then  --reg_epc CP0 14
      addr_a1 <= "00000";
      addr_a1 <= "00000";
   else
   else

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