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<b><font size=+2 color=#bf0000>Project: M-lite CPU core -- executes MIPS I(tm) opcodes</font></b><p><b><font size=+1>Details</font></b> <p>Category: <a href='/projects?category=microprocessor'>Microprocessor</a><br>Last updated: 6/2/2002<br>Created: 25/9/2001<br>Wishbone compliant core: No<br>Stage: Production/Stable<br>Mailing list: <a href='/forums/cores'>Cores</a><p><b><font size=+1>Description</font></b> <p>M-lite is a "clean room" VHDL implementation of a CPU. It supports the MIPS I(tm) instruction set with a two-stage pipeline. Interrupts and User Mode instructions are supported.
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<br>
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<br>MIPS I(tm) is a registered trademark of MIPS Technologies. MIPS Technologies does not endorse and is not associated with this project.
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<br><p><b><font size=+1>Block diagram</font></b> <p><p><center><img src='/cores/mips/cpu.gif' border=0></center><p><b><font size=+1>Example Instruction</font></b> <p>As an example, an ADD instruction would take the following steps:
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<br><ul>
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1.The "pc_next" entity would pass the program counter (PC) to the "mem_ctrl" entity. [First Stage of Pipeline]
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<br> 2."Mem_ctrl" passes the opcode to the "control" entity.
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<br> 3."Control" converts the 32-bit opcode to a 60-bit VLWI opcode and sends control signals to the other entities.
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<br> 4.Based on the rs_index and rt_index control signals, "reg_bank" sends the 32-bit reg_source and reg_target to "bus_mux".
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<br> 5.Based on the a_source and b_source control signals, "bus_mux" multiplexes reg_source onto a_bus and reg_target onto b_bus.
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<br> 6.Based on the alu_func control signals, "alu" adds the values from a_bus and b_bus and places the result on c_bus.
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<br> 7.Based on the c_source control signals, "bus_bux" multiplexes c_bus onto reg_dest.
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<br> 8.Based on the rd_index control signal, "reg_bank" saves reg_dest into the correct register.
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<br></ul><p><b><font size=+1>Features</font></b> <p>The CPU is implemented as a two-stage pipeline with step #1 in the first stage and steps #2-8 occurring the second stage. Most instructions take one clock cycle. Interrupts are supported. A four cycle memory write is also supported for non-clocked memories.
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<br>
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<br>There are several control lines not shown in the diagram. A pause (wait-state) line will cause the pipeline to pause if the multiplication results are accessed before the multiplication is complete. <br><p><b><font size=+1>Supporting Documentation</font></b> <p>The implementation is based on information found in:
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<br>
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<br><ul><li>"MIPS RISC Architecture" by Gerry Kane and Joe Heinrich and
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</li><li>"The Designer's Guide to VHDL" by Peter J. Ashenden
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</li></ul>
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In addition, the MIPS I(tm) instruction set can be found by going to <a href="http://www.mips.com/">http://www.mips.com/</a> and then following the links to "Documentation", "Architecture Programming Publications for MIPS32(tm)", and "MIPS32(TM) Architecture for Programmers Volume II: The MIPS32(TM) Instruction Set".
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<br><p><b><font size=+1>Tools</font></b> <p>The tools used include VHDL Synopsys, ModelTech, the free VHDL simulator from <a href="http://www.symphonyeda.com/">Symphony</a>, and the <a href="/cores/mips/Gccmips.zip">GCC compiler</a> (121 KB for Windows PC host, MIPS(tm) target; optimization -O doesn't work).
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<br>
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<br><p><b><font size=+1>Registers</font></b> <p>All of the registers are clocked by the single master clock. The registers used in the design are grouped by entity and listed below:
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<br>
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<br><pre>
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<br> mem_ctrl
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<br> ===========================================
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<br> | Register Name | Type | Width |
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<br> ===========================================
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<br> | next_opcode_reg | Flip-flop | 32 |
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<br> | opcode_reg | Flip-flop | 32 |
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<br> | setup_done_reg | Flip-flop | 1 |
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<br> ===========================================
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<br>
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<br> mlite_cpu
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<br> ===========================================
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<br> | Register Name | Type | Width |
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<br> ===========================================
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<br> | intr_signal | Flip-flop | 1 |
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<br> | reset_reg | Flip-flop | 1 |
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<br> ===========================================
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<br>
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<br> mult
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<br> ===========================================
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<br> | Register Name | Type | Width |
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<br> ===========================================
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<br> | answer_reg | Flip-flop | 32 |
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<br> | count_reg | Flip-flop | 6 |
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<br> | do_div_reg | Flip-flop | 1 |
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<br> | do_signed_reg | Flip-flop | 1 |
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<br> | reg_a | Flip-flop | 32 |
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<br> | reg_b | Flip-flop | 64 |
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<br> ===========================================
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<br>
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<br> pc_next
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<br> ===========================================
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<br> | Register Name | Type | Width |
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<br> ===========================================
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<br> | pc_reg | Flip-flop | 30 |
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<br> ===========================================
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<br>
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<br> reg_bank (configured to optionally used dual port memory)
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<br> ===========================================
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<br> | Register Name | Type | Width |
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<br> ===========================================
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<br> | reg00_reg | Flip-flop | 32 |
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<br> | ... |
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<br> | reg31_reg | Flip-flop | 32 |
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<br> | reg_status_reg | Flip-flop | 1 |
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<br> ===========================================
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<br>
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<br></pre><br><p><b><font size=+1>Preliminary Synthesis</font></b> <p>The CPU core was synthesized for 0.13 um line widths with a predicted area less than 0.2 millimeters squared. The predicted maximum latency was less than 6 ns for a maximum clock speed of 150 MHz.
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<br>
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<br>A preliminary synthesis yields the following cells and die area. If one assumes that a standard cell is composed of three gates, then this is approximately a 20K gate design. It is interesting to note that the register bank requires over 60% of the area.
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<br><pre>
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<br> Block ports nets cells cell_area ~% delay(ns)
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<br> ------ ----- ---- ----- --------- --- ---------
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<br> alu 101 919 850 7503 12 1.11
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<br> bus_mux 283 672 486 4906 8 0.35
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<br> control 93 296 263 2250 4 0.29
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<br> mem_ctrl 271 455 318 3299 5 0.95
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<br> mult 101 1111 1043 9342 15 0.72
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<br> pc_next 94 277 215 1756 3 0.15
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<br> reg_bank 116 2650 2599 39477 62 1.02
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<br> shifter 71 423 384 3026 5 1.51
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<br> mlite_cpu 201 555 45 63888 100 5.61
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<br>
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<br> total 1331 7358 6203
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<br>
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<br></pre><br><p><b><font size=+1>List of Files</font></b> <p><ul>
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<table border="2" style="border-color:Black;border-collapse:collapse;">
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<tr>
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<td>FILE</td>
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<td>PURPOSE</td>
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</td><tr>
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</tr><tr>
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<td>makefile</td>
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<td>Makefile for the PC based VHDL simulator</td>
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</tr><tr>
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<td>code.txt</td>
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<td>Input opcodes for the test bench -- test.exe "converted"</td>
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</tr><tr>
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<td>alu.vhd</td>
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<td>Arithmetic Logic Unit</td>
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</tr><tr>
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<td>bus_mux.vhd</td>
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<td>BUS Multiplex Unit</td>
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</tr><tr>
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<td>control.vhd</td>
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<td>Opcode Decoder</td>
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</tr><tr>
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<td>mem_ctrl.vhd</td>
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<td>Memory Controller</td>
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</tr><tr>
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<td>mlite_cpu.vhd</td>
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<td>Top Level VHDL for M-lite CPU</td>
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</tr><tr>
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<td>mlite_pack.vhd</td>
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<td>Constants and Functions Package</td>
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</tr><tr>
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<td>mult.vhd</td>
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<td>Multiplication and Division Unit</td>
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</tr><tr>
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<td>pc_next.vhd</td>
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<td>Program Counter Unit</td>
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</tr><tr>
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<td>ram.vhd</td>
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<td>RAM for the Test Bench</td>
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</tr><tr>
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<td>reg_bank.vhd</td>
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<td>Register Bank for 32, 32-bit Registers</td>
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</tr><tr>
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<td>shifter.vhd</td>
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<td>Shifter Unit</td>
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</tr><tr>
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<td>tbench.vhd</td>
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<td>Test Bench that uses mlite_vpu.vhd and ram.vhd</td>
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</tr><tr>
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</tr><tr>
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<td>makefile</td>
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<td>Makefile for the PC for creating "code.txt"</td>
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</tr><tr>
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<td>boot.asm</td>
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<td>Initializes $gp and $sp, clears .bss</td>
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</tr><tr>
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<td>opcodes.asm</td>
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<td>Tests all the MIPS I(tm) opcodes</td>
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</tr><tr>
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<td>convert.c</td>
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<td>Converts test.exe to code.txt</td>
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</tr><tr>
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<td>mlite.c</td>
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<td>Simulates the CPU in software</td>
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</tr><tr>
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<td>test.c</td>
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<td>Test program (opcodes) for the M-lite CPU</td>
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</tr><tr>
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<td>pi.c</td>
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<td>Calculates the first 16 digits of PI</td>
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</tr><tr>
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<td>count.c</td>
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<td>Test program that counts using words</td>
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</tr><tr>
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<td>output.txt</td>
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<td>Output from the test bench</td>
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</tr><tr>
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<td>index.shtml</td>
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<td>Old copy of this help file</td>
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</tr><tr>
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<td>cpu.gif</td>
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<td>Block Diagram</td>
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</tr>
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</table>
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</ul>
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<p><b><font size=+1>Downloads</font></b> <p><table border=0 cellpadding=0 cellspacing=0 bgcolor='#000000' width=100%><tr><td><table border=0 cellpadding=3 cellspacing=1 width=100%><tr bgcolor='#c0e0ff'><td valign=top><b>Date</b></td><td valign=top><b>Description</b></td><td valign=top><b>Link</b></td></tr><tr bgcolor='#ffffff'><td valign=top>6/2/2002</td><td valign=top>Entire M-lite project (~50 KB)<br></td><td valign=top><a href='/cgi-bin/cvsget.cgi/mips'>mips</a></td></tr></table></td></tr></table><p><b><font size=+1>Convert</font></b> <p>The program "convert" changes the file "test.exe" into the HEX file "code.txt". The register $gp is initialized, and the .bss segment is cleared.
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<br><p><b><font size=+1>Big/Little Endian</font></b> <p>The M-lite CPU operates in Big Endian mode by default. To operate in Little Endian mode, change "little_endian" from "00" to "11" in the file mem_ctrl.vhd. <br><p><b><font size=+1>Legal Notice</font></b> <p><font color=red>MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS Technologies, Inc. MIPS Technologies does not endorse and is not associated with this project. If you use this core you are responsible for all legal issues. This "clean room" implementation of a CPU which executes MIPS(tm) opcodes does not negate MIPS Technologies, Inc. of their trademark, copyrights, or patents....
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<br>
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<br>Free for commercial and non-commercial use as long as the author and warning notices are maintained.
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<br>
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<br>This software is provided by Steve Rhoads "as is" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed. In no event shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or consequential damages (including, but not limited to, procurement of substitute goods or services; loss of use, data, or profits; or business interruption) however caused and on any theory of liability, whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way out of the use of this software, even if advised of the possibility of such damage.
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<br></font><br><p><b><font size=+1>Bus Interface</font></b> <p>All signals are active high. Writing to memory normally takes four cycles to meet address hold times. Addresses with mem_address(31)='1' take two cycles (assumed to be clocked). Below are the signals for writing a character to address 0xffff:
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<br>
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<br><pre>
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<br> entity mlite_cpu is
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<br> port(clk : in std_logic;
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<br> reset_in : in std_logic;
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<br> intr_in : in std_logic;
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<br>
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<br> mem_address : out std_logic_vector(31 downto 0);
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<br> mem_data_w : out std_logic_vector(31 downto 0);
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<br> mem_data_r : in std_logic_vector(31 downto 0);
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<br> mem_byte_sel: out std_logic_vector(3 downto 0);
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<br> mem_write : out std_logic;
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<br> mem_pause : in std_logic);
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<br> end; --entity mlite_cpu
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<br>
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<br>
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<br> mem_write
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<br> interrupt mem_byte_sel
|
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<br> reset mem_pause
|
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<br> ns mem_address m_data_w m_data_r
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<br> ===========================================
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<br> 6700 0 0 0 000002A4 ZZZZZZZZ A0AE0000 0 0 ( fetch write opcode)
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<br> 6800 0 0 0 000002B0 ZZZZZZZZ 0443FFF6 0 0 (1 fetch NEXT opcode)
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<br> 6900 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 0 (2 address hold)
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<br> 7000 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 1 (3 write the low byte)
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<br> 7100 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 0 (4 address hold)
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<br> 7200 0 0 0 000002B4 ZZZZZZZZ 00441806 0 0 ( execute NEXT opcode)
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<br>
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<br></pre><br><p><b><font size=+1>Status</font></b> <p><ul><li>All MIPS I(tm) instructions are implemented and tested with the following limitations (exceptions not supported; all 32-bit memory accesses must be long word aligned)
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</li><li>See "opcodes.asm" for regression test.
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</li><li>Tested with several C programs: Calculating PI; Prime Numbers; Showing Numbers Using Words.
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</li><li>Supports Interrupts
|
|
</li><li>Runs in a Xilinx FPGA
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</li></ul><p><b><font size=+1>Maintainers</font></b> <p><ul><li><a href='/people/rhoads'>Steve Rhoads</a></li></ul><p>
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<table cellspacing=0 cellpadding=6 border=0><tr><td><a href="/forums/post?to=1b5dbe2b2026ae49ee163366fae4d693">webmaster</a></td></tr></table>
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<table cellspacing=0 cellpadding=4 border=0><tr><td><center>Administrative contact: <a href="http://www.opencores.org/forums/post?to=2ee116c5a2d2e9ecceb4351ce864dc7b">administration@opencores.org</a></td></tr><tr><td>Copyright ©1999-2001 OPENCORES.ORG. All rights reserved.</td></tr></table>
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