URL https://opencores.org/ocsvn/plasma/plasma/trunk

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[/] [plasma/] [tags/] [V3_0/] [vhdl/] [mlite_cpu.vhd] - Diff between revs 124 and 128

Rev 124	Rev 128
Line 145...	Line 145...
`begin --architecture`	`begin --architecture`

`pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);`	`pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);`
`pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;`	`pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;`
`pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;`	`pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;`
`nullify_op <= '1' when (pc_source = from_lbranch and take_branch = '0')`	`nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')`
`or intr_signal = '1'`	`or intr_signal = '1'`
`else '0';`	`else '0';`
`c_bus <= c_alu or c_shift or c_mult;`	`c_bus <= c_alu or c_shift or c_mult;`
`reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';`	`reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';`

Line 283...	Line 283...
`u8_mult: mult`	`u8_mult: mult`
`generic map (adder_type => adder_type,`	`generic map (adder_type => adder_type,`
`mult_type => mult_type)`	`mult_type => mult_type)`
`port map (`	`port map (`
`clk => clk,`	`clk => clk,`
	`reset_in => reset,`
`a => a_busD,`	`a => a_busD,`
`b => b_busD,`	`b => b_busD,`
`mult_func => mult_funcD,`	`mult_func => mult_funcD,`
`c_mult => c_mult,`	`c_mult => c_mult,`
`pause_out => pause_mult);`	`pause_out => pause_mult);`