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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- NOTE: MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS
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-- NOTE: MIPS(tm) and MIPS I(tm) are registered trademarks of MIPS
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-- Technologies. MIPS Technologies does not endorse and is not
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-- Technologies. MIPS Technologies does not endorse and is not
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-- associated with this project.
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-- associated with this project.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Top level VHDL document that ties the eight other entities together.
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-- Top level VHDL document that ties the nine other entities together.
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-- Executes most MIPS I(tm) opcodes. Based on information found in:
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--
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-- Executes all MIPS I(tm) opcodes but exceptions and non-aligned
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-- memory accesses. Based on information found in:
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-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
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-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
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-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
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-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
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--
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-- The CPU is implemented as a two or three stage pipeline.
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-- An add instruction would take the following steps (see cpu.gif):
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-- An add instruction would take the following steps (see cpu.gif):
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-- 1. The "pc_next" entity would have previously passed the program
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-- Stage #1:
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-- counter (PC) to the "mem_ctrl" entity.
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-- 1. The "pc_next" entity passes the program counter (PC) to the
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-- "mem_ctrl" entity which fetches the opcode from memory.
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-- Stage #2:
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-- 2. "Mem_ctrl" passes the opcode to the "control" entity.
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-- 2. "Mem_ctrl" passes the opcode to the "control" entity.
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-- 3. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode
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-- 3. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode
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-- and sends control signals to the other entities.
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-- and sends control signals to the other entities.
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-- 4. Based on the rs_index and rt_index control signals, "reg_bank"
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-- 4. Based on the rs_index and rt_index control signals, "reg_bank"
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-- sends the 32-bit reg_source and reg_target to "bus_mux".
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-- sends the 32-bit reg_source and reg_target to "bus_mux".
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-- 5. Based on the a_source and b_source control signals, "bus_mux"
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-- 5. Based on the a_source and b_source control signals, "bus_mux"
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-- multiplexes reg_source onto a_bus and reg_target onto b_bus.
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-- multiplexes reg_source onto a_bus and reg_target onto b_bus.
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-- Stage #3:
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-- 6. Based on the alu_func control signals, "alu" adds the values
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-- 6. Based on the alu_func control signals, "alu" adds the values
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-- from a_bus and b_bus and places the result on c_bus.
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-- from a_bus and b_bus and places the result on c_bus.
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-- 7. Based on the c_source control signals, "bus_bux" multiplexes
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-- 7. Based on the c_source control signals, "bus_bux" multiplexes
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-- c_bus onto reg_dest.
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-- c_bus onto reg_dest.
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-- 8. Based on the rd_index control signal, "reg_bank" saves
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-- 8. Based on the rd_index control signal, "reg_bank" saves
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-- reg_dest into the correct register.
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-- reg_dest into the correct register.
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-- The CPU is implemented as a two/three stage pipeline with step #1 in
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-- the first stage and steps #2-#8 occuring the second stage. When
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-- operating with a three stage pipeline, steps #6-#8 occur in the
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-- third stage.
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--
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--
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-- Writing to high memory where a(31)='1' takes four cycles to meet RAM
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-- All signals are active high. Writing to high memory where a(31)='1'
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-- address hold times.
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-- takes five cycles to meet RAM address hold times.
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-- Addresses with a(31)='0' are assumed to be clocked and take two cycles.
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-- Addresses with a(31)='0' are assumed to be clocked and take three cycles.
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-- Here are the signals for writing a character to address 0xffff:
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-- Here are the signals for writing a character to address 0xffff:
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--
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--
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-- mem_write
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-- intr_in mem_pause
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-- interrupt mem_byte_sel
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-- reset_in mem_write
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-- reset mem_pause
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-- clk mem_byte_sel
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-- ns mem_address m_data_w m_data_r
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-- ns mem_address m_data_r m_data_w
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-- ===========================================
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-- =============================================
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-- 6700 0 0 0 000002A4 ZZZZZZZZ A0AE0000 0 0 ( fetch write opcode)
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-- 3000 1 0 0 0000002C A2820000 ZZZZZZZZ 0 0 0 (0 fetch write opcode)
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-- 6800 0 0 0 000002B0 ZZZZZZZZ 0443FFF6 0 0 (1 fetch NEXT opcode)
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-- 3050 0 0 0 0000002C A2820000 ZZZZZZZZ 0 0 0
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-- 6900 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 1 (2 write the low byte)
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-- 3100 1 0 0 00000030 340A0041 ZZZZZZZZ 0 0 0 (1 execute write opcode)
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-- 7000 0 0 0 000002B4 ZZZZZZZZ 00441806 0 0 ( execute NEXT opcode)
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-- 3150 0 0 0 00000030 340A0041 ZZZZZZZZ 0 0 0
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-- 3200 1 0 0 00000030 340A0041 ZZZZZZZZ 0 0 0 (2 calculating address)
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-- 3250 0 0 0 00000030 340A0041 ZZZZZZZZ 0 0 0
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-- 3300 1 0 0 0000FFFF ZZZZZZZZ 6A6A6A6A 1 1 0 (3 writing value)
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-- 3350 0 0 0 0000FFFF ZZZZZZZZ 6A6A6A6A 1 1 0
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-- 3400 1 0 0 00000034 340B0042 ZZZZZZZZ 0 0 0
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-- 3450 0 0 0 00000034 340B0042 ZZZZZZZZ 0 0 0
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--
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-- Program:
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-- addr value opcode args
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-- ===================================
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-- 002c a2820000 sb $v0,0($s4)
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-- 0030 340a0041 li $t2,0x41
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-- 0034 340b0042 li $t3,0x42
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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entity mlite_cpu is
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entity mlite_cpu is
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generic(memory_type : string := "ALTERA";
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generic(memory_type : string := "ALTERA";
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pipeline_stages : natural := 3;
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pipeline_stages : natural := 3;
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accurate_timing : boolean := false);
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accurate_timing : boolean := true);
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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intr_in : in std_logic;
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intr_in : in std_logic;
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mem_address : out std_logic_vector(31 downto 0);
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mem_address : out std_logic_vector(31 downto 0);
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begin --architecture
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begin --architecture
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pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
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pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
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pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
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pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
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pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
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pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
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nullify_op <= '1' when pc_source = from_lbranch and
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nullify_op <= '1' when pc_source = from_lbranch and take_branchD = '0' else
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(take_branchD = '0' or branch_func = branch_yes) else
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'0';
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'0';
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c_bus <= c_alu or c_shift or c_mult;
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c_bus <= c_alu or c_shift or c_mult;
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reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
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reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
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--synchronize reset and interrupt pins
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--synchronize reset and interrupt pins
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intr_proc: process(clk, reset_in, intr_in, intr_enable, pc_source, pc, pause_any)
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intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
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pc_source, pc, pause_any)
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begin
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begin
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if reset_in = '1' then
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if reset_in = '1' then
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reset_reg <= "0000";
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reset_reg <= "0000";
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if reset_reg /= "1111" then
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if reset_reg /= "1111" then
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