| Line 300... |
Line 300... |
branch_func : in branch_function_type;
|
branch_func : in branch_function_type;
|
take_branch : out std_logic);
|
take_branch : out std_logic);
|
end component;
|
end component;
|
|
|
component alu
|
component alu
|
generic(adder_type : string := "GENERIC";
|
generic(adder_type : string := "DEFAULT";
|
alu_type : string := "GENERIC");
|
alu_type : string := "DEFAULT");
|
port(a_in : in std_logic_vector(31 downto 0);
|
port(a_in : in std_logic_vector(31 downto 0);
|
b_in : in std_logic_vector(31 downto 0);
|
b_in : in std_logic_vector(31 downto 0);
|
alu_function : in alu_function_type;
|
alu_function : in alu_function_type;
|
c_alu : out std_logic_vector(31 downto 0));
|
c_alu : out std_logic_vector(31 downto 0));
|
end component;
|
end component;
|
|
|
component shifter
|
component shifter
|
generic( shifter_type : string := "GENERIC" );
|
generic( shifter_type : string := "DEFAULT" );
|
port(value : in std_logic_vector(31 downto 0);
|
port(value : in std_logic_vector(31 downto 0);
|
shift_amount : in std_logic_vector(4 downto 0);
|
shift_amount : in std_logic_vector(4 downto 0);
|
shift_func : in shift_function_type;
|
shift_func : in shift_function_type;
|
c_shift : out std_logic_vector(31 downto 0));
|
c_shift : out std_logic_vector(31 downto 0));
|
end component;
|
end component;
|
|
|
component mult
|
component mult
|
generic (
|
generic (
|
adder_type : string := "GENERIC";
|
adder_type : string := "DEFAULT";
|
mult_type : string := "GENERIC");
|
mult_type : string := "DEFAULT");
|
port (
|
port (
|
clk : in std_logic;
|
clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
a, b : in std_logic_vector(31 downto 0);
|
a, b : in std_logic_vector(31 downto 0);
|
mult_func : in mult_function_type;
|
mult_func : in mult_function_type;
|
| Line 361... |
Line 361... |
pause_pipeline : out std_logic);
|
pause_pipeline : out std_logic);
|
end component;
|
end component;
|
|
|
component mlite_cpu
|
component mlite_cpu
|
generic(memory_type : string := "ALTERA";
|
generic(memory_type : string := "ALTERA";
|
mult_type : string := "GENERIC";
|
mult_type : string := "DEFAULT";
|
shifter_type : string := "GENERIC";
|
shifter_type : string := "DEFAULT";
|
pipeline_stages : natural := 3);
|
pipeline_stages : natural := 3);
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
intr_in : in std_logic;
|
intr_in : in std_logic;
|
|
|
| Line 377... |
Line 377... |
mem_write : out std_logic;
|
mem_write : out std_logic;
|
mem_pause : in std_logic);
|
mem_pause : in std_logic);
|
end component;
|
end component;
|
|
|
component ram
|
component ram
|
generic(memory_type : string := "GENERIC");
|
generic(memory_type : string := "DEFAULT");
|
port(clk : in std_logic;
|
port(clk : in std_logic;
|
mem_byte_sel : in std_logic_vector(3 downto 0);
|
mem_byte_sel : in std_logic_vector(3 downto 0);
|
mem_write : in std_logic;
|
mem_write : in std_logic;
|
mem_address : in std_logic_vector(31 downto 0);
|
mem_address : in std_logic_vector(31 downto 0);
|
mem_data_w : in std_logic_vector(31 downto 0);
|
mem_data_w : in std_logic_vector(31 downto 0);
|
| Line 398... |
Line 398... |
uart_write : out std_logic;
|
uart_write : out std_logic;
|
pause : out std_logic);
|
pause : out std_logic);
|
end component; --uart
|
end component; --uart
|
|
|
component plasma
|
component plasma
|
generic(memory_type : string := "GENERIC";
|
generic(memory_type : string := "DEFAULT";
|
log_file : string := "UNUSED");
|
log_file : string := "UNUSED");
|
port(clk_in : in std_logic;
|
port(clk_in : in std_logic;
|
reset_in : in std_logic;
|
reset_in : in std_logic;
|
intr_in : in std_logic;
|
intr_in : in std_logic;
|
|
|
