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https://opencores.org/ocsvn/plasma/plasma/trunk
[/] [plasma/] [tags/] [V3_0/] [vhdl/] [plasma.vhd] - Diff between revs 55 and 105
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Rev 55 |
Rev 105 |
Line 38... |
Line 38... |
signal mem_write : std_logic;
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signal mem_write : std_logic;
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signal mem_pause : std_logic;
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signal mem_pause : std_logic;
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signal mem_pause_uart : std_logic;
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signal mem_pause_uart : std_logic;
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signal uart_sel : std_logic;
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signal uart_sel : std_logic;
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begin --architecture
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begin --architecture
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mem_pause <= mem_pause_in or mem_pause_uart;
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uart_sel <= '1' when mem_address(12 downto 0) = ONES(12 downto 0) and
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uart_sel <= '1' when mem_address(12 downto 0) = ONES(12 downto 0) and mem_byte_sel /= "0000" else
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mem_byte_sel /= "0000" else '0';
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'0';
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mem_data <= mem_data_r;
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mem_data <= mem_data_r;
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mem_pause <= (mem_pause_in and not uart_sel) or mem_pause_uart;
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u1_cpu: mlite_cpu
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u1_cpu: mlite_cpu
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generic map (memory_type => memory_type)
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generic map (memory_type => memory_type)
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PORT MAP (
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PORT MAP (
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clk => clk_in,
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clk => clk_in,
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