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https://opencores.org/ocsvn/plasma/plasma/trunk
[/] [plasma/] [tags/] [V3_0/] [vhdl/] [reg_bank.vhd] - Diff between revs 12 and 24
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| Rev 12 |
Rev 24 |
| Line 15... |
Line 15... |
use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mips_pack.all;
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use work.mips_pack.all;
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entity reg_bank is
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entity reg_bank is
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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rs_index : in std_logic_vector(5 downto 0);
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rs_index : in std_logic_vector(5 downto 0);
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rt_index : in std_logic_vector(5 downto 0);
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rt_index : in std_logic_vector(5 downto 0);
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rd_index : in std_logic_vector(5 downto 0);
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rd_index : in std_logic_vector(5 downto 0);
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reg_source_out : out std_logic_vector(31 downto 0);
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reg_source_out : out std_logic_vector(31 downto 0);
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reg_target_out : out std_logic_vector(31 downto 0);
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reg_target_out : out std_logic_vector(31 downto 0);
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| Line 77... |
Line 78... |
else
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else
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addr_b <= rd_index(4 downto 0);
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addr_b <= rd_index(4 downto 0);
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end if;
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end if;
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rd_index = "101100" then
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if reset_in = '1' or rd_index = "101110" then --reg_epc CP0 14
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reg_status <= reg_dest_new(0);
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elsif rd_index = "101110" then --reg_epc CP0 14
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reg_status <= '0'; --disable interrupts
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reg_status <= '0'; --disable interrupts
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elsif rd_index = "101100" then
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reg_status <= reg_dest_new(0);
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end if;
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end if;
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end if;
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end if;
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intr_enable <= reg_status;
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intr_enable <= reg_status;
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end process;
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end process;
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