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Line 34... |
-- Different FPGAs and ASICs need different implementations.
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-- Different FPGAs and ASICs need different implementations.
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-- Choose one of the RAM implementations below.
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-- Choose one of the RAM implementations below.
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-- I need feedback on this section!
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-- I need feedback on this section!
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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architecture ram_block of reg_bank is
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architecture ram_block of reg_bank is
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signal reg_status : std_logic;
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signal intr_enable_reg : std_logic;
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type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
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type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
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--controls access to dual-port memories
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--controls access to dual-port memories
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signal addr_a1, addr_a2, addr_b : std_logic_vector(4 downto 0);
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signal addr_a1, addr_a2, addr_b : std_logic_vector(4 downto 0);
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signal data_out1, data_out2 : std_logic_vector(31 downto 0);
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signal data_out1, data_out2 : std_logic_vector(31 downto 0);
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| Line 47... |
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-- signal sig_true : std_logic := '1';
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-- signal sig_true : std_logic := '1';
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-- signal zero_sig : std_logic_vector(15 downto 0) := ZERP(15 downto 0);
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-- signal zero_sig : std_logic_vector(15 downto 0) := ZERP(15 downto 0);
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begin
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begin
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reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
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reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
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reg_status, data_out1, data_out2, reset_in)
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intr_enable_reg, data_out1, data_out2, reset_in)
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begin
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begin
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--setup for first dual-port memory
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--setup for first dual-port memory
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if rs_index = "101110" then --reg_epc CP0 14
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if rs_index = "101110" then --reg_epc CP0 14
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addr_a1 <= "00000";
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addr_a1 <= "00000";
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else
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else
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addr_a1 <= rs_index(4 downto 0);
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addr_a1 <= rs_index(4 downto 0);
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end if;
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end if;
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case rs_index is
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case rs_index is
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when "000000" => reg_source_out <= ZERO;
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when "000000" => reg_source_out <= ZERO;
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when "101100" => reg_source_out <= ZERO(31 downto 1) & reg_status;
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when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
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when "111111" => reg_source_out <= ZERO(31 downto 8) & "00110000"; --intr vector
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when "111111" => reg_source_out <= ZERO(31 downto 8) & "00110000"; --intr vector
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when others => reg_source_out <= data_out1;
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when others => reg_source_out <= data_out1;
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end case;
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end case;
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--setup for second dual-port memory
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--setup for second dual-port memory
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Line 81... |
addr_b <= "00000";
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addr_b <= "00000";
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else
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else
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addr_b <= rd_index(4 downto 0);
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addr_b <= rd_index(4 downto 0);
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end if;
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end if;
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if rising_edge(clk) then
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if reset_in = '1' then
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if reset_in = '1' or rd_index = "101110" then --reg_epc CP0 14
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intr_enable_reg <= '0';
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reg_status <= '0'; --disable interrupts
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elsif rising_edge(clk) then
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if rd_index = "101110" then --reg_epc CP0 14
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intr_enable_reg <= '0'; --disable interrupts
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elsif rd_index = "101100" then
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elsif rd_index = "101100" then
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reg_status <= reg_dest_new(0);
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intr_enable_reg <= reg_dest_new(0);
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end if;
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end if;
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end if;
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end if;
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intr_enable <= reg_status;
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intr_enable <= intr_enable_reg;
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end process;
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end process;
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------------------------------------------------------------
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------------------------------------------------------------
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-- Pick only ONE of the dual-port RAM implementations below!
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-- Pick only ONE of the dual-port RAM implementations below!
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| Line 125... |
Line 127... |
-- According to the Xilinx answers database record #4075 this
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-- According to the Xilinx answers database record #4075 this
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-- architecture may cause Synplify to infer synchronous dual-port
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-- architecture may cause Synplify to infer synchronous dual-port
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-- RAM using RAM16x1D.
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-- RAM using RAM16x1D.
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dual_port_mem:
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dual_port_mem:
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if memory_type = "DUAL_PORT" generate
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if memory_type = "DUAL_PORT" generate
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ram_proc: process(clk, addr_a1, addr_a2, addr_b, reg_dest_new,
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ram_proc2: process(clk, addr_a1, addr_a2, addr_b, reg_dest_new,
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write_enable)
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write_enable)
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variable dual_port_ram1 : ram_type;
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variable dual_port_ram1 : ram_type;
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variable dual_port_ram2 : ram_type;
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variable dual_port_ram2 : ram_type;
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begin
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begin
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data_out1 <= dual_port_ram1(conv_integer(addr_a1));
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data_out1 <= dual_port_ram1(conv_integer(addr_a1));
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