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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Control 4KB unified cache that uses the upper 4KB of the 8KB
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-- Control 4KB unified cache that uses the upper 4KB of the 8KB
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-- internal RAM. Only lowest 2MB of DDR is cached.
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-- internal RAM. Only lowest 2MB of DDR is cached.
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-- Only include file for Xilinx FPGAs.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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library UNISIM;
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library UNISIM;
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signal cache_tag_reg : std_logic_vector(8 downto 0);
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signal cache_tag_reg : std_logic_vector(8 downto 0);
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signal cache_tag_out : std_logic_vector(8 downto 0);
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signal cache_tag_out : std_logic_vector(8 downto 0);
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signal cache_we : std_logic;
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signal cache_we : std_logic;
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begin
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begin
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cache_proc: process(clk, reset, mem_busy, cache_address, cache_we,
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cache_proc: process(clk, reset, mem_busy, cache_address,
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state_reg, state, state_next,
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state_reg, state, state_next,
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address_next, byte_we_next, cache_tag_in, --Stage1
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address_next, byte_we_next, cache_tag_in, --Stage1
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cache_tag_reg, cache_tag_out, --Stage2
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cache_tag_reg, cache_tag_out, --Stage2
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cpu_address) --Stage3
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cpu_address) --Stage3
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begin
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begin
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case state_reg is
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case state_reg is
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when STATE_CHECK =>
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when STATE_CHECK => --cache idle
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cache_checking <= '0';
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cache_checking <= '0';
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cache_miss <= '0';
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cache_miss <= '0';
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state <= STATE_CHECK;
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state <= STATE_CHECK;
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when STATE_CHECKING =>
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when STATE_CHECKING => --current read in cached range, check if match
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cache_checking <= '1';
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cache_checking <= '1';
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if cache_tag_out /= cache_tag_reg or cache_tag_out = ONES(8 downto 0) then
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if cache_tag_out /= cache_tag_reg or cache_tag_out = ONES(8 downto 0) then
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cache_miss <= '1';
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cache_miss <= '1';
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state <= STATE_MISSED;
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state <= STATE_MISSED;
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else
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else
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cache_miss <= '0';
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cache_miss <= '0';
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state <= STATE_CHECK;
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state <= STATE_CHECK;
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end if;
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end if;
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cache_we <= '0';
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when STATE_MISSED => --current read cache miss
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when STATE_MISSED =>
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cache_checking <= '0';
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cache_checking <= '0';
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cache_miss <= '1';
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cache_miss <= '1';
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cache_we <= '1';
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if mem_busy = '1' then
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if mem_busy = '1' then
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state <= STATE_MISSED;
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state <= STATE_MISSED;
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else
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else
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state <= STATE_CHECK;
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state <= STATE_CHECK;
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end if;
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end if;
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when STATE_WRITING =>
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when STATE_WRITING => --writing back to cache and memory
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cache_checking <= '0';
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cache_checking <= '0';
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cache_miss <= '0';
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cache_miss <= '0';
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cache_we <= '0';
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if mem_busy = '1' then
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if mem_busy = '1' then
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state <= STATE_WRITING;
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state <= STATE_WRITING;
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else
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else
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state <= STATE_CHECK;
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state <= STATE_CHECK;
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end if;
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end if;
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when others =>
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when others =>
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cache_checking <= '0';
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cache_checking <= '0';
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cache_miss <= '0';
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cache_miss <= '0';
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cache_we <= '0';
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state <= STATE_CHECK;
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state <= STATE_CHECK;
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end case; --state
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end case; --state
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if state = STATE_CHECK and state_reg /= STATE_MISSED then
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if state = STATE_CHECK then --check if next access in cached range
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cache_address <= '0' & address_next(11 downto 2);
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cache_address <= '0' & address_next(11 downto 2);
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if address_next(30 downto 21) = "0010000000" then --first 2MB of DDR
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if address_next(30 downto 21) = "0010000000" then --first 2MB of DDR
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cache_check <= '1';
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cache_check <= '1';
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if byte_we_next = "0000" then
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if byte_we_next = "0000" then --read cycle
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cache_we <= '0';
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cache_we <= '0';
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state_next <= STATE_CHECKING;
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state_next <= STATE_CHECKING; --need to check if match
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else
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else
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cache_we <= '1';
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cache_we <= '1'; --update cache tag
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state_next <= STATE_WRITING;
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state_next <= STATE_WRITING;
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end if;
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end if;
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else
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else
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cache_check <= '0';
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cache_check <= '0';
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cache_we <= '0';
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cache_we <= '0';
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state_next <= STATE_CHECK;
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state_next <= STATE_CHECK;
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end if;
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end if;
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else
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else
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cache_address <= '0' & cpu_address(11 downto 2);
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cache_address <= '0' & cpu_address(11 downto 2);
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cache_check <= '0';
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cache_check <= '0';
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if state = STATE_MISSED then
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cache_we <= '1'; --update cache tag
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else
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cache_we <= '0';
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end if;
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state_next <= state;
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state_next <= state;
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end if;
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end if;
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if byte_we_next = "0000" or byte_we_next = "1111" then
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if byte_we_next = "0000" or byte_we_next = "1111" then --read or 32-bit write
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cache_tag_in <= address_next(20 downto 12);
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cache_tag_in <= address_next(20 downto 12);
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else
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else
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cache_tag_in <= ONES(8 downto 0); --invalid tag
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cache_tag_in <= ONES(8 downto 0); --invalid tag
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end if;
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end if;
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