| Line 25... |
Line 25... |
address_next : in std_logic_vector(31 downto 2);
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address_next : in std_logic_vector(31 downto 2);
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byte_we_next : in std_logic_vector(3 downto 0);
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byte_we_next : in std_logic_vector(3 downto 0);
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cpu_address : in std_logic_vector(31 downto 2);
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cpu_address : in std_logic_vector(31 downto 2);
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mem_busy : in std_logic;
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mem_busy : in std_logic;
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cache_check : out std_logic; --Stage1: address_next in first 2MB DDR
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cache_access : out std_logic; --access 4KB cache
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cache_checking : out std_logic; --Stage2: cache checking
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cache_checking : out std_logic; --checking if cache hit
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cache_miss : out std_logic); --Stage2-3: cache miss
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cache_miss : out std_logic); --cache miss
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end; --cache
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end; --cache
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architecture logic of cache is
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architecture logic of cache is
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subtype state_type is std_logic_vector(1 downto 0);
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subtype state_type is std_logic_vector(1 downto 0);
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constant STATE_CHECK : state_type := "00";
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constant STATE_IDLE : state_type := "00";
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constant STATE_CHECKING : state_type := "01";
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constant STATE_CHECKING : state_type := "01";
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constant STATE_MISSED : state_type := "10";
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constant STATE_MISSED : state_type := "10";
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constant STATE_WRITING : state_type := "11";
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constant STATE_WAITING : state_type := "11";
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signal state_reg : state_type;
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signal state_reg : state_type;
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signal state : state_type;
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signal state : state_type;
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signal state_next : state_type;
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signal state_next : state_type;
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| Line 56... |
Line 56... |
cache_tag_reg, cache_tag_out, --Stage2
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cache_tag_reg, cache_tag_out, --Stage2
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cpu_address) --Stage3
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cpu_address) --Stage3
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begin
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begin
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case state_reg is
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case state_reg is
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when STATE_CHECK => --cache idle
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when STATE_IDLE => --cache idle
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cache_checking <= '0';
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cache_checking <= '0';
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cache_miss <= '0';
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cache_miss <= '0';
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state <= STATE_CHECK;
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state <= STATE_IDLE;
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when STATE_CHECKING => --current read in cached range, check if match
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when STATE_CHECKING => --current read in cached range, check if match
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cache_checking <= '1';
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cache_checking <= '1';
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if cache_tag_out /= cache_tag_reg or cache_tag_out = ONES(8 downto 0) then
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if cache_tag_out /= cache_tag_reg or cache_tag_out = ONES(8 downto 0) then
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cache_miss <= '1';
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cache_miss <= '1';
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state <= STATE_MISSED;
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state <= STATE_MISSED;
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else
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else
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cache_miss <= '0';
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cache_miss <= '0';
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state <= STATE_CHECK;
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state <= STATE_IDLE;
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end if;
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end if;
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when STATE_MISSED => --current read cache miss
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when STATE_MISSED => --current read cache miss
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cache_checking <= '0';
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cache_checking <= '0';
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cache_miss <= '1';
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cache_miss <= '1';
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if mem_busy = '1' then
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if mem_busy = '1' then
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state <= STATE_MISSED;
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state <= STATE_MISSED;
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else
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else
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state <= STATE_CHECK;
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state <= STATE_WAITING;
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end if;
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end if;
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when STATE_WRITING => --writing back to cache and memory
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when STATE_WAITING => --waiting for memory access to complete
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cache_checking <= '0';
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cache_checking <= '0';
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cache_miss <= '0';
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cache_miss <= '0';
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if mem_busy = '1' then
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if mem_busy = '1' then
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state <= STATE_WRITING;
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state <= STATE_WAITING;
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else
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else
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state <= STATE_CHECK;
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state <= STATE_IDLE;
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end if;
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end if;
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when others =>
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when others =>
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cache_checking <= '0';
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cache_checking <= '0';
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cache_miss <= '0';
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cache_miss <= '0';
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state <= STATE_CHECK;
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state <= STATE_IDLE;
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end case; --state
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end case; --state
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if state = STATE_CHECK then --check if next access in cached range
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if state = STATE_IDLE then --check if next access in cached range
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cache_address <= '0' & address_next(11 downto 2);
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cache_address <= '0' & address_next(11 downto 2);
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if address_next(30 downto 21) = "0010000000" then --first 2MB of DDR
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if address_next(30 downto 21) = "0010000000" then --first 2MB of DDR
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cache_check <= '1';
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cache_access <= '1';
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if byte_we_next = "0000" then --read cycle
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if byte_we_next = "0000" then --read cycle
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cache_we <= '0';
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cache_we <= '0';
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state_next <= STATE_CHECKING; --need to check if match
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state_next <= STATE_CHECKING; --need to check if match
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else
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else
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cache_we <= '1'; --update cache tag
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cache_we <= '1'; --update cache tag
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state_next <= STATE_WRITING;
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state_next <= STATE_WAITING;
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end if;
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end if;
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else
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else
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cache_check <= '0';
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cache_access <= '0';
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cache_we <= '0';
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cache_we <= '0';
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state_next <= STATE_CHECK;
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state_next <= STATE_IDLE;
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end if;
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end if;
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else
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else
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cache_address <= '0' & cpu_address(11 downto 2);
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cache_address <= '0' & cpu_address(11 downto 2);
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cache_check <= '0';
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cache_access <= '0';
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if state = STATE_MISSED then
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if state = STATE_MISSED then
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cache_we <= '1'; --update cache tag
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cache_we <= '1'; --update cache tag
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else
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else
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cache_we <= '0';
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cache_we <= '0';
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end if;
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end if;
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| Line 125... |
Line 125... |
else
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else
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cache_tag_in <= ONES(8 downto 0); --invalid tag
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cache_tag_in <= ONES(8 downto 0); --invalid tag
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end if;
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end if;
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if reset = '1' then
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if reset = '1' then
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state_reg <= STATE_CHECK;
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state_reg <= STATE_IDLE;
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cache_tag_reg <= ZERO(8 downto 0);
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cache_tag_reg <= ZERO(8 downto 0);
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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state_reg <= state_next;
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state_reg <= state_next;
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if state = STATE_CHECK and state_reg /= STATE_MISSED then
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if state = STATE_IDLE and state_reg /= STATE_MISSED then
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cache_tag_reg <= cache_tag_in;
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cache_tag_reg <= cache_tag_in;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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