| Line 46... |
Line 46... |
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
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E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
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end; --entity eth_dma
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end; --entity eth_dma
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|
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architecture logic of eth_dma is
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architecture logic of eth_dma is
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signal rec_clk : std_logic_vector(1 downto 0); --receive
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signal rec_clk : std_logic_vector(1 downto 0); --receive
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signal rec_valid : std_logic;
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signal rec_latch : std_logic_vector(3 downto 0);
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signal rec_store : std_logic_vector(31 downto 0); --to DDR
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signal rec_store : std_logic_vector(31 downto 0); --to DDR
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signal rec_data : std_logic_vector(27 downto 0);
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signal rec_data : std_logic_vector(27 downto 0);
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signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
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signal rec_cnt : std_logic_vector(2 downto 0); --nibbles
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signal rec_words : std_logic_vector(13 downto 0);
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signal rec_words : std_logic_vector(13 downto 0);
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signal rec_dma : std_logic_vector(1 downto 0); --active & request
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signal rec_dma : std_logic_vector(1 downto 0); --active & request
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| Line 69... |
Line 67... |
begin --architecture
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begin --architecture
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|
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dma_proc: process(clk, reset, enable_eth, select_eth,
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dma_proc: process(clk, reset, enable_eth, select_eth,
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data_read, pause_in, mem_address, mem_byte_we, data_w,
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data_read, pause_in, mem_address, mem_byte_we, data_w,
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E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
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E_RX_CLK, E_RX_DV, E_RXD, E_TX_CLK,
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rec_clk, rec_valid, rec_latch, rec_store, rec_data,
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rec_clk, rec_store, rec_data,
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rec_cnt, rec_words, rec_dma, rec_done,
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rec_cnt, rec_words, rec_dma, rec_done,
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send_clk, send_read, send_data, send_cnt, send_words,
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send_clk, send_read, send_data, send_cnt, send_words,
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send_level, send_dma, send_enable)
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send_level, send_dma, send_enable)
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begin
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begin
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|
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if rising_edge(E_RX_CLK) then
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rec_valid <= E_RX_DV;
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rec_latch <= E_RXD;
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end if;
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if reset = '1' then
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if reset = '1' then
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rec_clk <= "00";
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rec_clk <= "00";
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rec_cnt <= "000";
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rec_cnt <= "000";
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rec_words <= ZERO(13 downto 0);
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rec_words <= ZERO(13 downto 0);
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rec_dma <= "00";
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rec_dma <= "00";
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| Line 97... |
Line 90... |
elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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|
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--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
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--Receive nibble on low->high E_RX_CLK. Send to DDR every 32 bits.
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rec_clk <= rec_clk(0) & E_RX_CLK;
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rec_clk <= rec_clk(0) & E_RX_CLK;
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if rec_clk = "01" and enable_eth = '1' then
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if rec_clk = "01" and enable_eth = '1' then
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if rec_valid = '1' or rec_cnt /= "000" then
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if E_RX_DV = '1' or rec_cnt /= "000" then
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if rec_cnt = "111" then
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if rec_cnt = "111" then
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rec_store <= rec_data & rec_latch;
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rec_store <= rec_data & E_RXD;
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rec_dma(0) <= '1'; --request DMA
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rec_dma(0) <= '1'; --request DMA
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end if;
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end if;
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rec_data <= rec_data(23 downto 0) & rec_latch;
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rec_data <= rec_data(23 downto 0) & E_RXD;
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rec_cnt <= rec_cnt + 1;
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rec_cnt <= rec_cnt + 1;
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end if;
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end if;
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end if;
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end if;
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|
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--Set transmit count or clear receive interrupt
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--Set transmit count or clear receive interrupt
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| Line 141... |
Line 134... |
--Pick which type of DMA operation: bit0 = request; bit1 = active
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--Pick which type of DMA operation: bit0 = request; bit1 = active
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if pause_in = '0' then
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if pause_in = '0' then
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if rec_dma(1) = '1' then
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if rec_dma(1) = '1' then
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rec_dma <= "00"; --DMA done
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rec_dma <= "00"; --DMA done
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rec_words <= rec_words + 1;
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rec_words <= rec_words + 1;
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if rec_valid = '0' then
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if E_RX_DV = '0' then
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rec_done <= '1';
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rec_done <= '1';
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end if;
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end if;
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elsif send_dma(1) = '1' then
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elsif send_dma(1) = '1' then
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send_dma <= "00";
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send_dma <= "00";
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send_words <= send_words + 1;
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send_words <= send_words + 1;
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