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https://opencores.org/ocsvn/plasma/plasma/trunk
[/] [plasma/] [trunk/] [vhdl/] [mem_ctrl.vhd] - Diff between revs 43 and 47
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Rev 43 |
Rev 47 |
Line 145... |
Line 145... |
end if;
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end if;
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else
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else
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if setup_state = STATE_FETCH then
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if setup_state = STATE_FETCH then
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pause := '1';
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pause := '1';
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byte_sel_next := "0000";
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byte_sel_next := "0000";
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if mem_pause = '0' then
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setup_state_next := STATE_ADDR;
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setup_state_next := STATE_ADDR;
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end if;
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elsif setup_state = STATE_ADDR then
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elsif setup_state = STATE_ADDR then
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address_next := address_data;
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address_next := address_data;
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if write_next ='1' and address_data(31) = '0' then
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if write_next ='1' and address_data(31) = '0' then
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pause := '1';
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pause := '1';
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byte_sel_next := "0000";
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byte_sel_next := "0000";
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if mem_pause = '0' then
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setup_state_next := STATE_WRITE; --4 cycle access
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setup_state_next := STATE_WRITE; --4 cycle access
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end if;
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else
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else
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if mem_pause = '0' then
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if mem_pause = '0' then
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opcode_next := next_opcode_reg;
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opcode_next := next_opcode_reg;
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setup_state_next := STATE_FETCH; --2 cycle access
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setup_state_next := STATE_FETCH; --2 cycle access
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end if;
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end if;
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Line 168... |
Line 172... |
end if;
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end if;
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elsif setup_state = STATE_PAUSE then
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elsif setup_state = STATE_PAUSE then
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address_next := address_data;
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address_next := address_data;
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byte_sel_next := "0000";
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byte_sel_next := "0000";
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opcode_next := next_opcode_reg;
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opcode_next := next_opcode_reg;
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if mem_pause = '0' then
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setup_state_next := STATE_FETCH;
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setup_state_next := STATE_FETCH;
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end if;
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end if;
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end if;
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end if;
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end if;
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if nullify_op = '1' then
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if nullify_op = '1' then
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opcode_next := ZERO; --NOP
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opcode_next := ZERO; --NOP
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end if;
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end if;
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if reset_in = '1' then
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if reset_in = '1' then
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