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[/] [plasma/] [trunk/] [vhdl/] [mlite_cpu.vhd] - Diff between revs 120 and 124

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Rev 120 Rev 124
Line 145... Line 145...
begin  --architecture
begin  --architecture
 
 
   pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
   pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
   pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
   pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
   pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
   pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
   nullify_op <= '1' when pc_source = from_lbranch and take_branch = '0' else '0';
   nullify_op <= '1' when (pc_source = from_lbranch and take_branch = '0')
 
                          or intr_signal = '1'
 
                          else '0';
   c_bus <= c_alu or c_shift or c_mult;
   c_bus <= c_alu or c_shift or c_mult;
   reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
   reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
 
 
   --synchronize reset and interrupt pins
   --synchronize reset and interrupt pins
   intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
   intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
      pc_source, pc, pause_any)
      pc_source, pc, pause_any)
   begin
   begin
      if reset_in = '1' then
      if reset_in = '1' then
         reset_reg <= "0000";
         reset_reg <= "0000";
 
         intr_signal <= '0';
      elsif rising_edge(clk) then
      elsif rising_edge(clk) then
         if reset_reg /= "1111" then
         if reset_reg /= "1111" then
            reset_reg <= reset_reg + 1;
            reset_reg <= reset_reg + 1;
         end if;
         end if;
 
 
         --don't try to interrupt a multi-cycle instruction
         --don't try to interrupt a multi-cycle instruction
 
         if pause_any = '0' then
         if intr_in = '1' and intr_enable = '1' and
         if intr_in = '1' and intr_enable = '1' and
               pc_source = from_inc4 and pc(2) = '0' and
                  pc_source = from_inc4 and pc(2) = '0' then
               pause_any = '0' then
 
            --the epc will be backed up one opcode (pc-4)
            --the epc will be backed up one opcode (pc-4)
            intr_signal <= '1';
            intr_signal <= '1';
         else
         else
            intr_signal <= '0';
            intr_signal <= '0';
         end if;
         end if;
      end if;
      end if;
 
 
 
      end if;
   end process;
   end process;
 
 
   u1_pc_next: pc_next PORT MAP (
   u1_pc_next: pc_next PORT MAP (
        clk          => clk,
        clk          => clk,
        reset_in     => reset,
        reset_in     => reset,

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