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signal pause_non_ctrl : std_logic;
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signal pause_non_ctrl : std_logic;
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signal pause_bank : std_logic;
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signal pause_bank : std_logic;
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signal nullify_op : std_logic;
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signal nullify_op : std_logic;
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signal intr_enable : std_logic;
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signal intr_enable : std_logic;
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signal intr_signal : std_logic;
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signal intr_signal : std_logic;
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signal exception_sig : std_logic;
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signal reset_reg : std_logic_vector(3 downto 0);
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signal reset_reg : std_logic_vector(3 downto 0);
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signal reset : std_logic;
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signal reset : std_logic;
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begin --architecture
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begin --architecture
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pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
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pause_any <= (mem_pause or pause_ctrl) or (pause_mult or pause_pipeline);
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pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
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pause_non_ctrl <= (mem_pause or pause_mult) or pause_pipeline;
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pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
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pause_bank <= (mem_pause or pause_ctrl or pause_mult) and not pause_pipeline;
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nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
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nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
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or intr_signal = '1'
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or intr_signal = '1' or exception_sig = '1'
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else '0';
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else '0';
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c_bus <= c_alu or c_shift or c_mult;
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c_bus <= c_alu or c_shift or c_mult;
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reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
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reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
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mem_address(1 downto 0) <= "00";
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mem_address(1 downto 0) <= "00";
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branch_func => branch_func,
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branch_func => branch_func,
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a_source_out => a_source,
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a_source_out => a_source,
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b_source_out => b_source,
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b_source_out => b_source,
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c_source_out => c_source,
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c_source_out => c_source,
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pc_source_out=> pc_source,
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pc_source_out=> pc_source,
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mem_source_out=> mem_source);
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mem_source_out=> mem_source,
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exception_out=> exception_sig);
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u4_reg_bank: reg_bank
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u4_reg_bank: reg_bank
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generic map(memory_type => memory_type)
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generic map(memory_type => memory_type)
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port map (
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port map (
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clk => clk,
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clk => clk,
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