| Line 15... |
Line 15... |
-- Executes all MIPS I(tm) opcodes but exceptions and non-aligned
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-- Executes all MIPS I(tm) opcodes but exceptions and non-aligned
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-- memory accesses. Based on information found in:
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-- memory accesses. Based on information found in:
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-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
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-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
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-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
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-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
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--
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--
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-- The CPU is implemented as a three or four stage pipeline.
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-- The CPU is implemented as a two or three stage pipeline.
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-- An add instruction would take the following steps (see cpu.gif):
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-- An add instruction would take the following steps (see cpu.gif):
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-- Stage #1:
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-- Stage #0:
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-- 1. The "pc_next" entity passes the program counter (PC) to the
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-- 1. The "pc_next" entity passes the program counter (PC) to the
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-- "mem_ctrl" entity which fetches the opcode from memory.
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-- "mem_ctrl" entity which fetches the opcode from memory.
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-- Stage #2:
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-- Stage #1:
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-- 2. The memory returns the opcode.
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-- 2. The memory returns the opcode.
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-- Stage #3:
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-- Stage #2:
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-- 3. "Mem_ctrl" passes the opcode to the "control" entity.
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-- 3. "Mem_ctrl" passes the opcode to the "control" entity.
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-- 4. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode
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-- 4. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode
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-- and sends control signals to the other entities.
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-- and sends control signals to the other entities.
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-- 5. Based on the rs_index and rt_index control signals, "reg_bank"
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-- 5. Based on the rs_index and rt_index control signals, "reg_bank"
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-- sends the 32-bit reg_source and reg_target to "bus_mux".
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-- sends the 32-bit reg_source and reg_target to "bus_mux".
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-- 6. Based on the a_source and b_source control signals, "bus_mux"
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-- 6. Based on the a_source and b_source control signals, "bus_mux"
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-- multiplexes reg_source onto a_bus and reg_target onto b_bus.
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-- multiplexes reg_source onto a_bus and reg_target onto b_bus.
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-- Stage #4 (part of stage #3 if using three stage pipeline):
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-- Stage #3 (part of stage #2 if using two stage pipeline):
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-- 7. Based on the alu_func control signals, "alu" adds the values
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-- 7. Based on the alu_func control signals, "alu" adds the values
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-- from a_bus and b_bus and places the result on c_bus.
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-- from a_bus and b_bus and places the result on c_bus.
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-- 8. Based on the c_source control signals, "bus_bux" multiplexes
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-- 8. Based on the c_source control signals, "bus_bux" multiplexes
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-- c_bus onto reg_dest.
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-- c_bus onto reg_dest.
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-- 9. Based on the rd_index control signal, "reg_bank" saves
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-- 9. Based on the rd_index control signal, "reg_bank" saves
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-- reg_dest into the correct register.
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-- reg_dest into the correct register.
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-- Stage #4b:
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-- Stage #3b:
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-- 10. Read or write memory if needed.
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-- 10. Read or write memory if needed.
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--
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--
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-- All signals are active high.
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-- All signals are active high.
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-- Here are the signals for writing a character to address 0xffff
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-- Here are the signals for writing a character to address 0xffff
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-- when using a three stage pipeline:
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-- when using a two stage pipeline:
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--
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--
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-- Program:
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-- Program:
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-- addr value opcode
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-- addr value opcode
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-- =============================
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-- =============================
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-- 3c: 00000000 nop
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-- 3c: 00000000 nop
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| Line 75... |
Line 75... |
entity mlite_cpu is
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entity mlite_cpu is
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generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
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generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
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mult_type : string := "DEFAULT"; --AREA_OPTIMIZED
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mult_type : string := "DEFAULT"; --AREA_OPTIMIZED
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shifter_type : string := "DEFAULT"; --AREA_OPTIMIZED
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shifter_type : string := "DEFAULT"; --AREA_OPTIMIZED
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alu_type : string := "DEFAULT"; --AREA_OPTIMIZED
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alu_type : string := "DEFAULT"; --AREA_OPTIMIZED
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pipeline_stages : natural := 3); --3 or 4
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pipeline_stages : natural := 2); --2 or 3
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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intr_in : in std_logic;
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intr_in : in std_logic;
|
|
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mem_address : out std_logic_vector(31 downto 0);
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mem_address : out std_logic_vector(31 downto 0);
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| Line 88... |
Line 88... |
mem_byte_we : out std_logic_vector(3 downto 0);
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mem_byte_we : out std_logic_vector(3 downto 0);
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mem_pause : in std_logic);
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mem_pause : in std_logic);
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end; --entity mlite_cpu
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end; --entity mlite_cpu
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|
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architecture logic of mlite_cpu is
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architecture logic of mlite_cpu is
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--When using a three stage pipeline "sigD <= sig".
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--When using a two stage pipeline "sigD <= sig".
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--When using a four stage pipeline "sigD <= sig when rising_edge(clk)",
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--When using a three stage pipeline "sigD <= sig when rising_edge(clk)",
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-- so sigD is delayed by one clock cycle.
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-- so sigD is delayed by one clock cycle.
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signal opcode : std_logic_vector(31 downto 0);
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signal opcode : std_logic_vector(31 downto 0);
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signal rs_index : std_logic_vector(5 downto 0);
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signal rs_index : std_logic_vector(5 downto 0);
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signal rt_index : std_logic_vector(5 downto 0);
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signal rt_index : std_logic_vector(5 downto 0);
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signal rd_index : std_logic_vector(5 downto 0);
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signal rd_index : std_logic_vector(5 downto 0);
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| Line 287... |
Line 287... |
b => b_busD,
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b => b_busD,
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mult_func => mult_funcD,
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mult_func => mult_funcD,
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c_mult => c_mult,
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c_mult => c_mult,
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pause_out => pause_mult);
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pause_out => pause_mult);
|
|
|
pipeline3: if pipeline_stages <= 3 generate
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pipeline2: if pipeline_stages <= 2 generate
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a_busD <= a_bus;
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a_busD <= a_bus;
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b_busD <= b_bus;
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b_busD <= b_bus;
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alu_funcD <= alu_func;
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alu_funcD <= alu_func;
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shift_funcD <= shift_func;
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shift_funcD <= shift_func;
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mult_funcD <= mult_func;
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mult_funcD <= mult_func;
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rd_indexD <= rd_index;
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rd_indexD <= rd_index;
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reg_destD <= reg_dest;
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reg_destD <= reg_dest;
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pause_pipeline <= '0';
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pause_pipeline <= '0';
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end generate; --pipeline2
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end generate; --pipeline2
|
|
|
pipeline4: if pipeline_stages > 3 generate
|
pipeline3: if pipeline_stages > 2 generate
|
--When operating in four stage pipeline mode, the following signals
|
--When operating in three stage pipeline mode, the following signals
|
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
|
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
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--c_source, and rd_index.
|
--c_source, and rd_index.
|
u9_pipeline: pipeline port map (
|
u9_pipeline: pipeline port map (
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
| Line 331... |
Line 331... |
c_source => c_source,
|
c_source => c_source,
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c_bus => c_bus,
|
c_bus => c_bus,
|
pause_any => pause_any,
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pause_any => pause_any,
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pause_pipeline => pause_pipeline);
|
pause_pipeline => pause_pipeline);
|
|
|
end generate; --pipeline4
|
end generate; --pipeline3
|
|
|
end; --architecture logic
|
end; --architecture logic
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No newline at end of file
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No newline at end of file
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