| Line 55... |
Line 55... |
-- 48: a0a40000 sb $a0,0($a1)
|
-- 48: a0a40000 sb $a0,0($a1)
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-- 4c: 00000000 nop
|
-- 4c: 00000000 nop
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-- 50: 00000000 nop
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-- 50: 00000000 nop
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--
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--
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-- intr_in mem_pause
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-- intr_in mem_pause
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-- reset_in mem_byte_we Stages
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-- reset_in byte_we Stages
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-- ns mem_address mem_data_w mem_data_r 40 44 48 4c 50
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-- ns address data_w data_r 40 44 48 4c 50
|
-- 3500 0 0 00000040 00000000 00000000 0 0 0
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-- 3600 0 0 00000040 00000000 34040041 0 0 1
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-- 3600 0 0 00000044 00000000 34040041 0 0 1 0
|
-- 3700 0 0 00000044 00000000 3405FFFF 0 0 2 1
|
-- 3700 0 0 00000048 00000000 3405FFFF 0 0 2 1 0
|
-- 3800 0 0 00000048 00000000 A0A40000 0 0 2 1
|
-- 3800 0 0 0000004C 00000000 A0A40000 0 0 2 1 0
|
-- 3900 0 0 0000004C 41414141 00000000 1 0 2 1
|
-- 3900 0 0 0000FFFC 41414141 00000000 1 0 2 1
|
-- 4000 0 0 0000FFFC 41414141 XXXXXX41 0 0 3 2
|
-- 4000 0 0 00000050 41414141 XXXXXX41 0 0 3 2 0
|
-- 4100 0 0 00000050 00000000 00000000 0 0 1
|
-- 4100 0 0 00000054 00000000 00000000 0 0 1
|
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
library ieee;
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library ieee;
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use work.mlite_pack.all;
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use work.mlite_pack.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
|
| Line 80... |
Line 79... |
pipeline_stages : natural := 2); --2 or 3
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pipeline_stages : natural := 2); --2 or 3
|
port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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intr_in : in std_logic;
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intr_in : in std_logic;
|
|
|
mem_address : out std_logic_vector(31 downto 0);
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address_next : out std_logic_vector(31 downto 2); --for synch ram
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mem_data_w : out std_logic_vector(31 downto 0);
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byte_we_next : out std_logic_vector(3 downto 0);
|
mem_data_r : in std_logic_vector(31 downto 0);
|
|
mem_byte_we : out std_logic_vector(3 downto 0);
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address : out std_logic_vector(31 downto 2);
|
|
byte_we : out std_logic_vector(3 downto 0);
|
|
data_w : out std_logic_vector(31 downto 0);
|
|
data_r : in std_logic_vector(31 downto 0);
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mem_pause : in std_logic);
|
mem_pause : in std_logic);
|
end; --entity mlite_cpu
|
end; --entity mlite_cpu
|
|
|
architecture logic of mlite_cpu is
|
architecture logic of mlite_cpu is
|
--When using a two stage pipeline "sigD <= sig".
|
--When using a two stage pipeline "sigD <= sig".
|
| Line 148... |
Line 150... |
nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
|
nullify_op <= '1' when (pc_source = FROM_LBRANCH and take_branch = '0')
|
or intr_signal = '1' or exception_sig = '1'
|
or intr_signal = '1' or exception_sig = '1'
|
else '0';
|
else '0';
|
c_bus <= c_alu or c_shift or c_mult;
|
c_bus <= c_alu or c_shift or c_mult;
|
reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
|
reset <= '1' when reset_in = '1' or reset_reg /= "1111" else '0';
|
mem_address(1 downto 0) <= "00";
|
|
|
|
--synchronize reset and interrupt pins
|
--synchronize reset and interrupt pins
|
intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
|
intr_proc: process(clk, reset_in, reset_reg, intr_in, intr_enable,
|
pc_source, pc_current, pause_any)
|
pc_source, pc_current, pause_any)
|
begin
|
begin
|
| Line 203... |
Line 204... |
mem_source => mem_source,
|
mem_source => mem_source,
|
data_write => reg_target,
|
data_write => reg_target,
|
data_read => c_memory,
|
data_read => c_memory,
|
pause_out => pause_ctrl,
|
pause_out => pause_ctrl,
|
|
|
mem_address => mem_address(31 downto 2),
|
address_next => address_next,
|
mem_data_w => mem_data_w,
|
byte_we_next => byte_we_next,
|
mem_data_r => mem_data_r,
|
|
mem_byte_we => mem_byte_we);
|
address => address,
|
|
byte_we => byte_we,
|
|
data_w => data_w,
|
|
data_r => data_r);
|
|
|
u3_control: control PORT MAP (
|
u3_control: control PORT MAP (
|
opcode => opcode,
|
opcode => opcode,
|
intr_signal => intr_signal,
|
intr_signal => intr_signal,
|
rs_index => rs_index,
|
rs_index => rs_index,
|
